Patents by Inventor William Bainbridge

William Bainbridge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110813
    Abstract: Techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. In various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (CMB). The target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. Communications via the CMB enable the target agent to determine, during a runtime of the network, whether a given initiator agent has been allocated an excessive number of credits, or an insufficient number of credits. In another embodiments, the target agent changes the distribution of credits to the initiator agents by allocating credits via the CMB.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Rahul Pal, Ashish Gupta, William Bainbridge
  • Publication number: 20240409599
    Abstract: The invention provides stabilized IL-18 polypeptides and methods of making and using the same.
    Type: Application
    Filed: May 21, 2024
    Publication date: December 12, 2024
    Applicant: Genentech, Inc.
    Inventors: Travis William Bainbridge, Beyza Bulutoglu Baykara, Jonathan Thomas Sockolosky
  • Publication number: 20230279067
    Abstract: The invention provides an effectorless immunoglobulin Fc protein, fusions of the effectorless Fc protein to a Flt3 ligand, and methods of using the same.
    Type: Application
    Filed: November 21, 2022
    Publication date: September 7, 2023
    Applicant: Genentech, Inc.
    Inventors: Yichin LIU, Christine Carine MOUSSION, Travis William BAINBRIDGE, lraj HOSSEINI, Gregory Alan LAZAR, Sivan COHEN, Christopher Charles KEMBALL, Jill M. SCHARTNER
  • Patent number: 11542308
    Abstract: The invention provides an effectorless immunoglobulin Fc protein, fusions of the effectorless Fc protein to a Flt3 ligand, and methods of using the same.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: January 3, 2023
    Assignee: Genentech, Inc.
    Inventors: Yichin Liu, Christine Carine Moussion, Travis William Bainbridge, Iraj Hosseini, Gregory Alan Lazar, Sivan Cohen, Christopher Charles Kemball, Jill M. Schartner
  • Publication number: 20220289803
    Abstract: The invention provides an effectoriess immunoglobulin Fc protein, fusions of the effectorless Fc protein to a Flt3 ligand, and methods of using the same.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 15, 2022
    Applicant: Genentech, Inc.
    Inventors: Yichin LIU, Christine Carine MOUSSION, Travis William BAINBRIDGE, Iraj HOSSEINI, Gregory Alan LAZAR, Sivan COHEN, Christopher Charles KEMBALL, Jill M. SCHARTNER
  • Publication number: 20200055896
    Abstract: Fluorescence resonance energy transfer (FRET) constructs comprising donor and acceptor fluorophore moieties, and a peptide linking the two, which is a substrate of the endopeptidase fibroblast activation protein (FAP). Also provided are isolated nucleic acids expressing the construct, cell lines comprising the nucleic acids, and kits comprising the construct. Further provided are methods of detecting FAP using the construct via FRET.
    Type: Application
    Filed: October 1, 2019
    Publication date: February 20, 2020
    Inventors: Travis William BAINBRIDGE, James Andrew ERNST, Junichiro SONODA
  • Patent number: 9846612
    Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: December 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Madan Krishnappa, Chinh Tran, Li Zhang, Alan Young, William Bainbridge, Bohuslav Rychlik
  • Publication number: 20170046218
    Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 16, 2017
    Inventors: MADAN KRISHNAPPA, CHINH TRAN, LI ZHANG, ALAN YOUNG, WILLIAM BAINBRIDGE
  • Publication number: 20170046219
    Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 16, 2017
    Inventors: MADAN KRISHNAPPA, CHINH TRAN, LI ZHANG, ALAN YOUNG, WILLIAM BAINBRIDGE, Bohuslav RYCHLIK
  • Publication number: 20050276346
    Abstract: A method for communication between a sender and a receiver, including receiving data in the form of an M-of-N code, where the M-of-N code includes a first component of length n1 and a second component of length n2; decoding data in which the first component is an m1-of-n1 code and the second component is an m2-of-n2 code; and decoding data in which the first component is an m3-of-n1 code where m1?m3 and the second component is an m4-of-n2 code where m2?m4.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 15, 2005
    Applicant: SILISTRIX LIMITED
    Inventor: William Bainbridge
  • Patent number: 5766395
    Abstract: A molded, self-supporting, composite part or panel for automotive and similar applications comprises a vapor impervious wood fiber filled polymeric (preferably polypropylene) sheet adhered to one major face of a corrugated paperboard medium and a layer of fibrous insulation (preferably glass fiber) or a second wood fiber filled polymeric sheet adhered to a second major face of the corrugated paperboard medium. The sheet and corrugated medium provide the structural strength for the composite and the fibrous insulation, when used, provides the composite with good sound absorption properties. The wood fiber filled polymeric sheet is formed during the molding process from a wood and polymeric fiber sheet. The heat and pressure of the molding process cause the polymeric fibers to melt and flow about the wood fibers to form the wood fiber filled sheet and bond the sheet securely to the corrugated medium.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: June 16, 1998
    Assignee: Johns Manville International, Inc.
    Inventors: David William Bainbridge, Mario Peter Tocci, Larry Maxwell Bauman
  • Patent number: 5057176
    Abstract: An automotive headliner comprised of a laminate of double corrugated paperboard. Perforations in all the sheets of the laminate except the back paperboard sheet improve the acoustical performance of the liner. A vapor barrier on the back sheet prevents entry of moisture into the laminate from the roof, and a layer of sound dampening material on the front face of the laminate improves the sound absorption of the laminate. The front corrugation is larger than the back corrugation. When molding the laminate it is first moisturized, then heat molded. Heat is applied until the laminate has regained its rigidity.
    Type: Grant
    Filed: October 10, 1989
    Date of Patent: October 15, 1991
    Assignee: Manville Corporation
    Inventor: William Bainbridge