Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A system and method for providing a minimum burst duration in accordance with a regional standard and/or requirement. One embodiment comprises a first interface (204) configured to receive data to be communicated, a memory (208) configured to store a value corresponding to a regional minimum duration, a processor (202) configured to generate a frame, configured to compare a duration of the generated frame with the regional minimum duration, configured to add at least one padding symbol to the generated frame to generate a second frame, the second frame having a duration at least equal to the regional minimum duration, and a second interface (206) configured to communicate the second frame onto a communication channel.

Abstract: A system and method for providing a minimum burst duration in accordance with a regional standard and/or requirement. One embodiment comprises a first interface (204) configured to receive data to be communicated, a memory (208) configured to store a value corresponding to a regional minimum duration, a processor (202) configured to generate a frame, configured to compare a duration of the generated frame with the regional minimum duration, configured to add at least one padding symbol to the generated frame to generate a second frame, the second frame having a duration at least equal to the regional minimum duration, and a second interface (206) configured to communicate the second frame onto a communication channel.

Abstract: Block modulus coding (BMC) systems implement block coding on non-binary modulus m symbols, where m is greater than 2. BMC systems can be used for, among other things, forward error correction (FEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data is represented by non-binary symbols that may be corrupted by burst errors. The block coding is preferably performed using a distributed arrangement of block encoders or decoders. A distributed block modulus encoder (DBME) encodes sequential source data symbols of modulus m with a plurality of sequential block encoders to produce interleaved parity codewords. The codewords utilize modulus m symbols where the medium can reliably resolve m symbol states.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase error. The timing phase error is then averaged and controls a phase locked loop (PLL). This PLL in turn controls a voltage-controlled oscillator, which handles the modem receiver timing. A centroid calculation can be included to bias the voltage-controlled oscillator to push the equalizer coefficients back to the ideal position. The system can be implemented in either a point-to-point modem environment or a multi-point environment, for example, but not limited to, MVL or DMT. The voltage-controlled oscillator may also be implemented to control transmitter timing, so that the central office modem and the remote modem will operate more-or-less synchronously, reducing the need for large equalizer corrections at either end.

Abstract: A composition and method for cleaning, sanitizing and maintaining contained bodies of water such as swimming pools, wading pools, fountains, ornamental ponds, etc. The composition includes pre-determined percentages of copper sulfate, zinc sulfate, and aluminum sulfate by weight. The composition and method reduce amounts of chlorine and an amount of labor associated with the cleaning, sanitization and maintenance of contained bodies of water.

Abstract: A tone ordered discrete multitone interleaver system and method, including a tone ordered interleaver and deinterleaver, are provided for efficiently communicating data despite noise affecting a Discrete Multitone modulation (DMT) system. The tone ordered discrete multitone interleaver forces interleaving of trellis encoded information by assigning a different number of bits to adjacent tones or adjacent tone pairs.

Abstract: Fractional bit rate encoding in a discrete multi-tone (DMT) communication environment allows the transmission of fractional bit rates, thus maximizing the use of signal-to-noise ratio (SNR) available on each of the DMT carriers, or tones, while maintaining a constant power density over the entire frequency spectrum.

Abstract: The present invention provides methods and apparatus for transmitting a data-bearing signal and a non-data-bearing signal. One embodiment comprises communicatively coupling a data-bearing signal during a first time period and communicatively coupling a non-data-bearing signal during a second time period. The data-bearing signal has a first PSD. The non-data-bearing signal has a second PSD substantially the same as the first over a range of frequencies. The non-data-bearing signal has characteristics facilitating echo cancellation. Another embodiment comprises a line interface and a transmitter coupled to the line interface, comprising a data encoder and a periodic signal generator. The encoder is configured to produce a data-bearing signal with a first PSD. The periodic signal generator is configured to produce a non-data-bearing signal with a second PSD. The second PSD is substantially the same as the first PSD over a first range of frequencies.

Abstract: A transient pre-emptor includes a processor configured to detect transients in a communications system. After the processor detects a transient in the communications system, it causes a data communications equipment to suspend or reduce data transmission during the occurrence of a subsequent transient.

Abstract: Several embodiments of a space diversity trellis interleaver system are provided for communicating data over a plurality of separate communication paths in order to inhibit distortion caused by impulse noise or other correlated noise and enhance the data transmission rate of data communications. The transmitter is designed to receive a plurality of data streams from data terminal equipment (DTE), which can be one or more devices. One or more convolutional encoders, preferably trellis encoders, encode each of the data streams. In an alternative embodiment, more than one trellis encoder is used to trellis encode each data stream. Data segments from the convolutionally encoded data streams are interleaved with a switch. The plurality of interleaved convolutionally-encoded data streams are modulated and transmitted onto a respective plurality of separate communication paths. At the receiver, the plurality of data streams is received from the separate communication paths and demodulated.

Abstract: A system and method for providing a minimum burst duration in accordance with a regional standard and/or requirement. One embodiment comprises a first interface (204) configured to receive data to be communicated, a memory (208) configured to store a value corresponding to a regional minimum duration, a processor (202) configured to generate a frame, configured to compare a duration of the generated frame with the regional minimum duration, configured to add at least one padding symbol to the generated frame to generate a second frame, the second frame having a duration at least equal to the regional minimum duration, and a second interface (206) configured to communicate the second frame onto a communication channel.

Abstract: A digital subscriber line (DSL) driver allows a transmitter to monitor its own transmit spectrum at the subscriber loop and adjust the transmit spectrum based on detected line conditions, affected by the presence of bridged taps or any other impedance variations. The transmit spectrum is preferably equalized so that all carriers, or tones, transmit using the same power and exhibit the same margin. The invention is applicable to DMT and single carrier modulation formats.

Abstract: A composition and method for cleaning, sanitizing and maintaining contained bodies of water such as swimming pools, wading pools, fountains, ornamental ponds, etc. The composition includes pre-determined percentages of copper sulfate, zinc sulfate, and aluminum sulfate by weight. The composition and method reduce amounts of chlorine and an amount of labor associated with the cleaning, sanitization and maintenance of contained bodies of water.

Abstract: A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system is implemented by using a calculation that finds the timing phase error. The timing phase error is then averaged and controls a phase locked loop (PLL). This PLL in turn controls a voltage-controlled oscillator, which handles the modem receiver timing. A centroid calculation can be included to bias the voltage-controlled oscillator to push the equalizer coefficients back to the ideal position. The system can be implemented in either a point-to-point modem environment or a multi-point environment, for example, but not limited to, MVL or DMT. The voltage-controlled oscillator may also be implemented to control transmitter timing, so that the central office modem and the remote modem will operate more-or-less synchronously, reducing the need for large equalizer corrections at either end.