Patents by Inventor WILLIAM BOWHILL

WILLIAM BOWHILL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Managing power consumption in a multi-core processor
    Patent number: 9075614
    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Eric Fetzer, Reid Riedlinger, Don Soltis, William Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
  • MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR
    Publication number: 20130232368
    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 5, 2013
    Inventors: ERIC FETZER, REID RIEDLINGER, DON SOLTIS, WILLIAM BOWHILL, SATISH SHRIMALI, KRISHNAKANTH SISTLA, EFRAIM ROTEM, RAKESH KUMAR, VIVEK GARG, ALON NAVEH, LOKESH SHARMA