Patents by Inventor William Brearley
William Brearley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11182531Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: GrantFiled: July 16, 2019Date of Patent: November 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shayak Banerjee, William Brearley
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Patent number: 11163934Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: GrantFiled: May 7, 2019Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shayak Banerjee, William Brearley
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Publication number: 20190340329Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Shayak Banerjee, William Brearley
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Patent number: 10395002Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: GrantFiled: January 5, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shayak Banerjee, William Brearley
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Publication number: 20190258774Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: Shayak Banerjee, William Brearley
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Patent number: 10339261Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: GrantFiled: December 8, 2015Date of Patent: July 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shayak Banerjee, William Brearley
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Publication number: 20170116368Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventors: Shayak Banerjee, William Brearley
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Patent number: 9607268Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: GrantFiled: March 15, 2016Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Shayak Banerjee, William Brearley
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Publication number: 20160196502Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: Shayak Banerjee, William Brearley
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Patent number: 9330223Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: GrantFiled: September 28, 2012Date of Patent: May 3, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shayak Banerjee, William Brearley
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Publication number: 20160092783Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: ApplicationFiled: December 8, 2015Publication date: March 31, 2016Inventors: Shayak Banerjee, William Brearley
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Publication number: 20140095124Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shayak Banerjee, William Brearley
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Patent number: 8584060Abstract: A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.Type: GrantFiled: November 16, 2012Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: William Brearley, Geng Han, Lars W. Liebmann
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Publication number: 20080088027Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.Type: ApplicationFiled: November 29, 2007Publication date: April 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: THEODORUS STANDAERT, WILLIAM BREARLEY, STEPHEN GRECO, SUJATHA SANKARAN
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Publication number: 20070032055Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.Type: ApplicationFiled: August 8, 2005Publication date: February 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Theodorus Standaert, William Brearley, Stephen Greco, Sujatha Sankaran
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Patent number: 6448169Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.Type: GrantFiled: December 21, 1995Date of Patent: September 10, 2002Assignee: International Business Machines CorporationInventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
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Patent number: 6149048Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.Type: GrantFiled: April 8, 1998Date of Patent: November 21, 2000Assignee: International Business Machines CorporationInventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
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Patent number: 6099935Abstract: An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position.Type: GrantFiled: December 15, 1995Date of Patent: August 8, 2000Assignee: International Business Machines CorporationInventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu