Patents by Inventor William Brearley

William Brearley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11182531
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 11163934
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Publication number: 20190340329
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 10395002
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Publication number: 20190258774
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 22, 2019
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 10339261
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Publication number: 20170116368
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 27, 2017
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 9607268
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shayak Banerjee, William Brearley
  • Publication number: 20160196502
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 7, 2016
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 9330223
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Publication number: 20160092783
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Application
    Filed: December 8, 2015
    Publication date: March 31, 2016
    Inventors: Shayak Banerjee, William Brearley
  • Publication number: 20140095124
    Abstract: A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shayak Banerjee, William Brearley
  • Patent number: 8584060
    Abstract: A method for decomposing design shapes in a design level into a plurality of target design levels is provided. Design shapes including first-type edges and second-type edges having different directions is provided for a design level. Inner vertices are identified and paired up. Vertices are classified into first-type vertices and second-type vertices. First mask level shapes are generated so as to touch the first-type vertices, and second mask level shapes are generated so as to tough the second-type vertices. Cut mask level shapes are generated to touch each first-type edges that are not over a second-type edge and to touch each second-type edges that are not over a first-type edge. Suitable edges are sized outward to ensure overlap among the various shapes. The design shapes are thus decomposed into first mask level shapes, the second mask level shapes, and the cut mask level shapes.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Geng Han, Lars W. Liebmann
  • Publication number: 20080088027
    Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
    Type: Application
    Filed: November 29, 2007
    Publication date: April 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: THEODORUS STANDAERT, WILLIAM BREARLEY, STEPHEN GRECO, SUJATHA SANKARAN
  • Publication number: 20070032055
    Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theodorus Standaert, William Brearley, Stephen Greco, Sujatha Sankaran
  • Patent number: 6448169
    Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
  • Patent number: 6149048
    Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.
    Type: Grant
    Filed: April 8, 1998
    Date of Patent: November 21, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
  • Patent number: 6099935
    Abstract: An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu