Abstract: A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.

Abstract: A method and system of executing duplicate copies of a program in lock step. Some illustrative embodiments are a computer system comprising a first processor executing a program, a second processor executing a duplicate copy of the program (the first processor and second processor executing their respective programs in lock step), a logic device coupled to the processors, and a shared device coupled to the processors through the logic device. The first processor presents to the logic device a first operation involving the shared device, and the second processor does not present an operation, or presents an operation that does not match the first operation. The logic device obtains a second operation from the second processor that matches the first operation, and wherein a single operation that matches the first and second operations is presented to the shared device.

Abstract: A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a second processor executing a duplicate copy of the program (but at different computational points in the program), and a shared main memory coupled to the first and second processors. When the processors each receive duplicate copies of an interrupt request, the processors are configured to bring their respective programs to the same computational points prior to servicing the interrupt request.

Abstract: A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a duplicate copy of the program in lock step with the first processor, and a logic device coupled to the processors. The logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program.

Abstract: A method and system of determining the execution point of programs executed in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor that executes a program, and a second processor that executes a duplicate copy of the program in lock step with the first processor. After receipt of a duplicate copy of an interrupt request by each processor, the first processor determines the execution point in its program relative to the execution point of the duplicate copy of the program executed by the second processor.

Abstract: A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.

Abstract: A method and system of servicing asynchronous interrupts in multiple processors executing a user program. Some of the exemplary embodiments may be a method comprising executing a user program on a first processor and a duplicate copy of the user program on a second processor, receiving an asynchronous interrupt by both the first and second processors, executing an interrupt service routine on the first processor at an agreed system call of the user program executed on the first processor, and executing an interrupt service routine on the second processor at the agreed system call of the user program executed on the second processor.

Abstract: A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.

Abstract: In a redundant-processor computing device, an error handling method comprises detecting equivalent disparity among processor elements of the computing device operating and responding to the detected equivalent disparity by evaluating secondary considerations of processor fidelity.

Abstract: Method and system of determining whether a user program has made a system level call and thus whether the user program is uncooperative with fault tolerant operation. Some exemplary embodiments may be a processor-based method comprising providing information from a first processor to a second processor (the information indicating that a user program executed on the first processor has not made a system level call in a predetermined amount of time), and determining by the first processor, using information from the second processor, whether a duplicate copy of the user program substantially simultaneously executed in the second processor has made a system level call in the predetermined amount of time.

Abstract: A plurality of redundant, loosely-coupled processor elements are operational as a logical processor. A logic detects a halt condition of the logical processor and, in response to the halt condition, reintegrates and commences operation in less than all of the processor elements leaving at least one processor element nonoperational. The logic also buffers data from the nonoperational processor element in the reloaded operational processor elements and writes the buffered data to storage for analysis.

Abstract: A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.

Abstract: A scalable clustered system includes a global fabric, and two or more cluster nodes interconnected via the global fabric. Each cluster node includes a node naming agent (NNA), a local fabric and one or more end nodes interconnected via the local fabric. The NNA is configured as a fully symmetrical translation device interposed between the local fabric and the global fabric. The NNA provides support for scaled clustering by transforming a local/global cluster address into a corresponding global/local cluster address for each packet in an outbound/inbound path. As embodied and broadly described herein, the invention relates also to a method including steps for scaling the clustered system. Additionally, the invention relates to a computer readable medium in a scalable clustered system that embodies computer program code configured to cause that system to perform steps for configuring and scaling that system.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device.

Abstract: Resets on a data processing system are targeted to specific locations of that processing system and have different effects. Some resets are transparent to instruction execution while other resets will interrupt the normal execution of instructions. In addition, in a multi-zone environment resets in one zone do not automatically propagate to the other zone; instead, each zone generates its own resets.

Abstract: A process for transferring data via DMA between a system resource and a controller via switching logic. During a setup write transaction, the switching logic is set up to enable DMA data to be transferred between a particular system memory and a selected system resource. The setup write transaction also is used to initialize the DMA byte counter. During a subsequent write transaction, DMA pointer registers are initialized with appropriate starting addresses. The controller then transmits a DMA start code and the system resource responds by transmitting an acknowledge code. At that time, DMA data is transmitted between the controller and the system resource via the switching logic.

Abstract: Method and apparatus for testing the operation of modules for use in a fault tolerant computing system that consists of two distinct computing zones. Diagnostic testing is performed when the system is powered on, the modules being subjected to module, zone and, if both zones are available, system diagnostic tests. Indications of faults detected during diagnostic testing are stored in an EEPROM on each module. Such fault indications can be cleared in the field by correcting the fault condition and successfully rerunning the diagnostic test during which the fault was detected. Indications of operating system detected faults are also stored in each module EEPROM. However, such fault indications are not field clearable.

Abstract: Method and apparatus for controlling initiating of bootstrap loading in a computer system having first and second discrete computing zones is disclosed. Each computing zone includes a status register for storing an operating system run (OSR) bit indicating that the zone has initiated bootstrap loading. A cable connects the computing zones to allow the first and second zones to read the status registers in the second and first zones, respectively. A CPU in each zone only enables initiation of bootstrap loading if the OSR bit in the other zone is not set.

Abstract: In a processing system having duplicate sets of elements, often called rails, to move rail unique data from one set of elements to the other set of elements, the unique data is moved to a scratchpad memory and then copied into a common memory after certain error checking is disabled.