Patents by Inventor William Budge
William Budge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7632737Abstract: A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.Type: GrantFiled: July 17, 2006Date of Patent: December 15, 2009Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, William Budge, Weimin Li
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Patent number: 7521354Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: November 4, 2005Date of Patent: April 21, 2009Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7501691Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: GrantFiled: August 28, 2007Date of Patent: March 10, 2009Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, William Budge
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Patent number: 7494894Abstract: A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.Type: GrantFiled: August 29, 2002Date of Patent: February 24, 2009Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, William Budge, Weimin Li
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Patent number: 7479440Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: GrantFiled: January 11, 2007Date of Patent: January 20, 2009Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, William Budge
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Publication number: 20070290294Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: ApplicationFiled: August 28, 2007Publication date: December 20, 2007Applicant: MICRON TECHNOLOGY, INC.Inventors: John Smythe, William Budge
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Patent number: 7273793Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.Type: GrantFiled: April 25, 2005Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, William Budge, Weimin Li, Gurtej S. Sandhu
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Patent number: 7271463Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: GrantFiled: December 10, 2004Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: John A. Smythe, III, William Budge
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Publication number: 20070111470Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: ApplicationFiled: January 11, 2007Publication date: May 17, 2007Applicant: MICRON TECHNOLGY, INC.Inventors: John Smythe, William Budge
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Patent number: 7219114Abstract: A method for an accurate approximation to Slerp function that is much faster to compute on current processors. Specifically, the present invention provides a method for obtaining an interpolated quaternion comprising forming a first product of a first quaternion and a first scaling function; forming a second product of a second quaternion and a second scaling function; and forming a sum of the first product and the second product, wherein the first scaling function is approximated by obtaining a first polynomial and wherein the second scaling function is approximated by obtaining a second polynomial, thus obtaining an interpolated quaternion that is in between the first quaternion and the second quaternion.Type: GrantFiled: April 10, 2002Date of Patent: May 15, 2007Assignee: Patent Purchase Manager, LLCInventor: William Budge
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Patent number: 7214979Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.Type: GrantFiled: August 25, 2004Date of Patent: May 8, 2007Assignee: Micron Technology, Inc.Inventors: William Budge, Gurtej S Sandhu, Christopher W Hill
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Patent number: 7202183Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.Type: GrantFiled: January 27, 2006Date of Patent: April 10, 2007Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, William Budge, Weimin Li, Gurtej S. Sandhu
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Patent number: 7192893Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.Type: GrantFiled: August 5, 2003Date of Patent: March 20, 2007Assignee: Micron Technology Inc.Inventors: William Budge, Gurtej S. Sandhu, Christopher W. Hill
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Publication number: 20060270240Abstract: A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.Type: ApplicationFiled: July 17, 2006Publication date: November 30, 2006Inventors: Neal Rueger, William Budge, Weimin Li
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Patent number: 7078356Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: March 19, 2002Date of Patent: July 18, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7067414Abstract: A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: March 27, 2000Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7067415Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: July 25, 2002Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Publication number: 20060134924Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.Type: ApplicationFiled: January 27, 2006Publication date: June 22, 2006Inventors: Neal Rueger, William Budge, Weimin Li, Gurtej Sandhu
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Publication number: 20060125043Abstract: A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.Type: ApplicationFiled: December 10, 2004Publication date: June 15, 2006Inventors: John Smythe, William Budge
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Patent number: 7056833Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.Type: GrantFiled: September 23, 2003Date of Patent: June 6, 2006Assignee: Micron Technology, Inc.Inventors: Neal R. Rueger, William Budge, Weimin Li, Gurtej S. Sandhu