Abstract: In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.

Abstract: In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.

Abstract: A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.

Abstract: An apparatus and method for manufacturing laminated parts from a plurality of laminas, in which the laminas for forming the laminated parts are blanked from strip stock material. The laminas and are then cut and stacked to form the laminated part. The apparatus includes a measuring device placed with the die element of the press, for accurately measuring the thickness of successive sections of the strip stock. A controller, such as a computer or a programmable logic controller, receives the thickness value of the strip stock sections from the measuring device. Means are also included which is activated by the controller to provide a compensation adjustment at selected locations upon the strip stock sections to counteract the measured thickness variations, and to control the stack height.

Abstract: An on-chip capacitor structure comprising a lower metal layer and an upper metal layer; an array of metal islands disposed between the lower and the upper metal layers; each island of the array of islands being electrically connected to either the lower layer or the upper layer such that no two adjacent islands are connected to the same layer.

Abstract: Disclosed are digital data receivers, methods and circuitry for differentiating between signals and data packets of varying physical layer protocols and frequencies transferred over a digital burst mode communications system, such as a packet-based LAN. Transitions in a received input signal to a squelch circuit start a counter which asserts one or more signals at various predetermined times from the transition. The absence or presence of the signal when the next transition in the input signal occurs indicates whether the input signal is less than or greater than a frequency associated with a particular predetermined time interval. When a predetermined number of transitions meeting a particular frequency requirement are received, the input signal is determined to be received at a particular frequency.