Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: A method for reducing power variations resulting from changes in processor workload includes communicating a power dip condition to a workload scheduler of a processor device in response to identifying the power dip condition. One or more target power workloads are assigned for execution at the processor device based at least in part on the power dip condition. Further, each of the one or more target power workloads is associated with a known power load.

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

Abstract: A processor surrogate (320/520) is adapted for use in a processing node (S1) of a multiprocessor data processing system (300/500) having a plurality of processing nodes (P0, S1) coupled together and to a plurality of input/output devices (330, 340, 350/530, 540, 550, 560) using corresponding communication links. The processor surrogate (320/520) includes a first port (372, 374/620, 622) comprising a first set of integrated circuit terminals adapted to be coupled to a first external communication link (370/590) for coupling (P0) of the plurality of processing nodes (310, 320/510, 520), a second port (382, 384/630, 632) comprising a second set of integrated circuit terminals adapted to be coupled to a second external communication link (380/592) for coupling to one (350/550) of the plurality of input/output devices (330, 340, 350/530, 540, 550, 560), and an interconnection circuit (390, 392/608, 612, 614) coupled between the first port (372, 374/620, 622) and the second port (382, 384/630, 632).

Abstract: A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.

Abstract: Packet switch protocol and circuitry for implementing it are disclosed. According to this protocol, a message transmitter of a first node in the network may send data through a data transmission link at a predetermined rate until it is signalled, via a control signal generated by a message receiver in a second node, to suspend its transmissions. The message transmitter may also be signalled to resume transmitting data. The message receiver includes a buffer memory in which messages are temporarily stored if their selected path is blocked as they pass through the network. When the amount of available space in the buffer is less than a preprogrammed threshold value, the message receiver generates the control signal to suspend message transmission. This threshold value leaves sufficient space in the buffer to store any data which may be in the pipeline between the transmitter and the receiver.

Abstract: A multiprocessing system is presented having a plurality of processing nodes interconnected together by a communication network, each processing node including a processor, responsive to user software running on the system, and an associated memory module, and capable under user control of dynamically partitioning each memory module into a global storage efficiently accessible by a number of processors connected to the network, and local storage efficiently accessible by its associated processor.

Abstract: A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data.

Abstract: A multiprocessing system is presented for dynamically partitioning a storage module into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including the interleaving of storage references output by a processor, under the control of that processor, and dynamically directing the storage references to first or second portions of the storage module.

Abstract: An energy saving DC-DC converter circuit is disclosed having two energy efficient means which operate in tandem, an energy conserving means (30, 8, 1) and a voltage doubling means (26). These energy efficient means are applied in combination with elements commonly found in DC-DC converter circuits, namely an AC voltage generator (2), a transformer (3) for stepping up the generated AC voltage, and means (31) for storing the converted DC voltage. The energy conserving means is connected to the DC voltage storage means (31). It comprises a resettable inhibit circuit (1) which cuts off the provision of DC voltage for conversion for a predetermined interval when the output of the converter exceeds a predetermined level. The voltage doubling means is reponsive to outputs of the inhibit circuit (1) of the energy conserving means and the AC voltage generator (2). It provides a phase inverted waveform of the generated AC voltage on one of two leads to the AC voltage step-up transformer (3).