Abstract: In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not part of the original design and state diagram of the unmodified state machine. In one embodiment, a method and apparatus is provided for dynamically reconfiguring a plurality of test circuits in re-useable modules on an IC without modifying the controller state machine in the re-usable module.

Abstract: The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66).

Abstract: A current monitor circuitry for detecting defects in a semiconductor device through performance of quiescent current testing. The circuitry for performing quiescent current testing may be implemented on chip or in an expendable portion of the wafer or a combination of both. In one embodiment, a quiescent current monitor unit interfaces with the circuit to be tested. The quiescent current monitor includes a sense amplifier and a level detector. The sense amplifier senses for a voltage differential and the level detector checks for a predetermined voltage rise. The voltage differences may be used for verification of specified circuit operations.

Abstract: An apparatus and method for generating pseudo-random test instructions for testing a microprocessor begins by providing an array of list structures (502 through 508). Each list structure (502 through 508) contains a list of instructions, a discipline field (34), a pick field (42) and a biasing field (36). A random list of instructions is created by using a list selection discipline field to determine which list (502 through 508) is selected. The discipline field in the particular list (502 through 508) is then used to determine a manner in which instructions are selected from a list of instructions contained within the list structure. The pick field indicates how many instructions are to be selected from each selected list structure using a method determined via the discipline field.

Abstract: A method for testing a test architecture in a circuit is accomplished by receiving or generating, based on the topology information for the circuit, a Boundary Scan Description Language (BSDL) description of the test architecture which is then verified for correct syntax, consistency, and standard compliance. Next, one or more tests are selected from a predetermined set of test methodologies, based on the type of testing to be performed. Self-checking test parameters are generated based on the BSDL description and the selected tests. Using these test parameters, a logic simulation algorithm tests the test architecture of the circuit and generates a report detailing any errors that are discovered.

Abstract: A data processing system (90) having a serial scan circuit (10). The serial scan circuit (10) has an address detector (12) for detecting and decoding M serially-provided address bits. Coupled to the address detector (12) is a clock generator (14) which is used for providing at least one derived clock signal. Coupled to the address detector (12) and the clock generator (14) is a serial scan chain (16) which is used to store N serially-provided data bits. A plurality of serial scan chains (10) is connected in a parallel configuration and used to form the data processing system (90). The M address bits and the N data bits are serially provided via a single conductor (24) in a time division multiplexed operation. Integrated circuit surface area is reduced by avoiding large address and data buses, and bus routing.

Abstract: In a data processor having an instruction which requires the loading of the contents of two (2) successive locations in the address space during respective bus cycles, test circuitry is provided to selectively force the processor to twice load the contents of the same location upon execution of the instruction. Using this special load double test instruction, the processor is able to detect more precisely when the contents of the memory location changes in value as a result of the activity of other circuitry.

Abstract: A method for performing a clear interrupt mask bit and wait operation in response to a single instruction. In responding to the clear and wait instruction a processor clears a condition code register, if desired, and then stacks a plurality of registers. Once the registers are stacked the processor is prepared to assume a wait for interrupt mode and will not respond to any other instruction until an interrupt occurs.

Abstract: A semaphore register for use in a peripheral controller includes a semaphore bit which when not set indicates the availability of a shared resource, an internal ownership bit which when set indicates ownership of the resource by a peripheral controller and an external ownership bit which when set indicates ownership of the resource by a host processor. If the semaphore is clear, upon receipt of a read signal from the peripheral controller, the semaphore bit and the internal ownership bit are set. Upon receipt of a read signal from the host processor, the semaphore bit and the external ownership bit are set. Arbitration logic includes means responsive to simultaneous reads by the host processor and the peripheral controller for indicating to the host processor that the resource is unavailable thus giving priority to the peripheral controller. The semaphore bit may be reset by write signals from either the peripheral controller or the host processor.

Abstract: A digital processor capable of responding to a sync instruction for high-speed synchronization of hardware and software is provided. The sync instruction places the procesor in a stopped state and lets the processor start up again only upon receipt of an interrupt. If the interrupt is disabled by being masked, the stopped state is simply cleared and the sequencing of instructions continues without vectoring to the interrupt service routine. However if the interrupt is not disabled, the processor will handle the interrupt just as it would if it were not in the stopped state. Upon return from the interrupt service routine, the stopped state is cleared and the sequencing of instructions continues. In this way, the sync instruction provides a mechanism for synchronizing software with hardware external to the processor without the delays associated with interrupts or busy-wait loops.