Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes reprogramming the lower page data to the memory cells prior to programming higher page data to the memory cells in a second pass of the multiple-pass programming operation.

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.

Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.

Abstract: Error correction systems and methods for improving sense matching conditions between hard-bit read (HBR) information and soft-bit read (SBR) information. For HBRs, a given set of sense conditions can include a discharged bit line of one or more cells that discharged during a previous HBR. For SBRs, a given set of sense conditions can include loading latches of the sense amplifiers for corresponding cells are with sense results of the previous SBR strobe when the corresponding cells discharged during a previous SBR strobe or loading the latches of the sense amplifiers with sense results of a previous HBR when the corresponding cells discharged during the previous HBR.

Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.

Abstract: Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. The control unit may be configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks during the program operation responsive to programming the first access line group of each of the plurality of subblocks.

Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.

Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.

Abstract: Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. The control unit may be configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks during the program operation responsive to programming the first access line group of each of the plurality of subblocks.

Abstract: Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.