Abstract: A circuit for selectively performing big-endian/little-endian data format conversion based on whether instructions or data are being transferred. The data and instructions are allocated to different regions in memory so that the big-endian/little-endian conversion is based on the source or destination address of the requested operation. Registers are provided to define a lower bound address and an upper bound address. In addition, a separate register is provided which indicates whether the data is stored between the lower bound and upper bound addresses or outside the lower bound and upper bound addresses. The registers are write addressable through the PCI configuration space, the memory space, and the I/O space, which allows the values in the registers to be changed dynamically during computer system operation.

Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol. The computer system is provided with the capability to recover from a loop hang condition resulting from an unresponsive communication link in an Arbitrated Loop. This capability is realized by providing a sense mechanism for detecting a no-change condition in the states associated with a controller arranged in the Arbitrated Loop.

Abstract: A modular computer chassis constructed with a center pluggable interface adapted for the modular mounting of components on opposite sides thereof. The chassis includes frontal and rear regions which are open and adapted for receipt of modular computer components therein for direct coupling to the center pluggable interface. An isolation frame is also provided within the chassis for physically and electrically isolating select components therein one from the other. A slidable mounting array is also provided for facilitating flexibility in the mounting of half height and one-third height disk drives adjacent to the center pluggable interface for flexibility in the design and utilization of the chassis of the present invention.

Abstract: A primary server/standby server network configuration according to the invention includes a primary server executing network operating system software and a standby server monitoring for the proper operation of the primary server, where both the primary server and the standby server are connected to a storage system. If the primary server fails, the standby server instructs the storage system to switch its hardware connections to the standby server, allowing the standby server to boot the operating system. This instruction is done via in-band signaling. Further, multiple primary servers can be backed up by a single standby server.

Abstract: A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor usage statistics of the FIFOs and to identify one of the FIFOs as a refill candidate buffer in the event of a miss which requires new data to be brought into one of the FIFOs. Each FIFO has a hit detector and a flush detector for comparing the address of a data request from the bus master with the address stored by each buffer for indicating FIFO hit or invalidate operations. Each FIFO also has a buffer selector to provide data from the buffer selected by the hit detector to the bus master if the selected FIFO buffer has not been invalidated by the invalidate address comparator. The buffer selector otherwise transferring the requested data from the memory to the refill candidate buffer and presenting new data from the refill candidate buffer to the bus master.

Abstract: A bridge for coupling two buses together utilizes a data buffer to act as a point of synchronization to provide effective data operations between the buses. The bridge includes master and slave capability on both buses and an arbiter for selecting between requests from bus masters on one bus. The data buffer includes a number of dual ported memories for write posting and read ahead operations. Each dual ported memory is allocated to a bus master of the one bus. The bridge allows data operations to each dual ported memory based on data or space availability of the memory. Simultaneous reading and writing capability on alternate buses is provided.

Abstract: A computer system which includes a circuit to monitor the PCI bus master grant lines and provide a disk drive activity signal if an appropriate grant line is activated. The PCI bus master grant lines are combined with mask signals, so that the grant lines not associated with a PCI bus master such as a SCSI controller are ignored. If an unmasked grant line is activated, a down counter is loaded. While the counter is at a non-zero value, a disk drive activity signal is provided. This disk drive activity signal is combined with other disk drive activity signals to drive the disk drive activity LED.

Abstract: A FIFO with locked exchange capability is disclosed. The FIFO has a memory for storing and retrieving data submissions, a write address generator and a read address generator for sequentially addressing the memory. A difference counter maintains the difference between the number of writes to the queue and reads from the queue. The net difference, as tracked by the counter is a measure of the FIFO utilization. To detect the queue full condition, a comparator compares the maximum FIFO stack depth against the counter output. The result of this comparison is latched and provided to a write strobe generator so that, in a subsequent write operation, if the FIFO is full, the write strobe from the producer is blocked and the data will not be written to the FIFO. Otherwise, the write strobe from the producer is passed to the memory. Additionally, a remaining space count is maintained in a status register.

Abstract: A bridge circuit for holding off primary interrupts signaling the completion of a block data transfer from a second bus to a system bus until the data has cleared the bridge circuit. The bridge circuit includes an interrupt control circuit for receiving up to seven primary interrupt signals corresponding to seven sets of bus grant-request lines on a second bus. Each bus grant-request set is assigned a data FIFO for synchronizing the transfer of data from the second bus to a system bus. The interrupt control circuit provides an interrupt to the system bus which corresponds to the primary interrupt only after the associated data FIFO is empty, thereby preventing data coherency problems in system memory.

Abstract: A primary server/standby server network configuration according to the invention includes a primary server executing network operating system software and a standby server monitoring for the proper operation of the primary server, where both the primary server and the standby server are connected to a storage system. If the primary server fails, the standby server instructs the storage system to switch its hardware connections to the standby server, allowing the standby server to boot the operating system. This instruction is done via in-band signaling. Further, multiple primary servers can be backed up by a single standby server.

Abstract: A computer system which includes a circuit to monitor the PCI bus master grant lines and provide a disk drive activity signal if an appropriate grant line is activated. The PCI bus master grant lines are combined with mask signals, so that the grant lines not associated with a PCI bus master such as a SCSI controller are ignored. If an unmasked grant line is activated, a down counter is loaded. While the counter is at a non-zero value, a disk drive activity signal is provided. This disk drive activity signal is combined with other disk drive activity signals to drive the disk drive activity LED.

Abstract: A system for detecting the presence and size of a SCSI device on a SCSI bus and terminating the SCSI bus accordingly. A SCSI controller is capable of driving two branches of a SCSI bus, each branch having a different data size. When the SCSI controller is at the end of a SCSI chain, termination is enabled, otherwise termination is disabled. Termination is performed on the portions of the SCSI data bus requiring termination based on the presence and size of SCSI devices on the branches used.

Abstract: Computer system which varies the number of read requests outstanding to hard disk drives based on the mix of sequential and random requests. If a sequential request is received, a limited number of requests are allowed to be outstanding. If the requests are random, a growing number of read requests can be outstanding as the random requests continue, until a maximum number of write requests are allowed to be outstanding.

Abstract: A method for improving SCSI controller operations by actively patching SCSI processor instructions. In a first case, tag values assigned to queues for tagged queue operation are a multiple of the SCSI processor jump instruction length. When reselected, the tag value is patched or overwritten as the least significant byte of the address of a jump instruction. The upper bytes point to the beginning of a jump table. Each entry in the jump table is a jump instruction to the sequence for a particular queue or thread. Thus simple entry is made to the desired thread without a conditional branch tree. In a second case, special SCSI operations are directly handled by the host device driver and the SCSI processor only performs conventional data transfers and similar operations. The device driver patches the message length of the SCSI processor code to an illegal value, so that an illegal instruction develops, prompting the host device driver to perform the operation at a register level.