Abstract: A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.

Abstract: Example implementations relate to a server node shutdown. For example, a system includes a control module and a secondary power supply. The control module includes a detect engine to detect an even that triggers a sequenced shutdown of a server node and prevent execution of the sequenced shutdown and execution of a data transfer. The control module also includes an initiate engine to initiate a data backup process, by a basic input/output system (BIOS) of the server node, to write data from a volatile memory location of the server node to a non-volatile memory location of the server node. The secondary power supply is to support the data backup process.

Abstract: A test and diagnostics circuit, methods and systems are described. An example test and diagnostics circuit includes a controller and a power monitor coupled to the controller. A load switch on the test and diagnostics circuit selectably implements a load from among multiple load values to test a computing and/or data storage system. The test and diagnostics circuit includes circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the system.

Abstract: According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.

Abstract: A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.

Abstract: Example implementations relate to a server node shutdown. For example, a system includes a control module and a secondary power supply. The control module includes a detect engine to detect an even that triggers a sequenced shutdown of a server node and prevent execution of the sequenced shutdown and execution of a data transfer. The control module also includes an initiate engine to initiate a data backup process, by a basic input/output system (BIOS) of the server node, to write data from a volatile memory location of the server node to a non-volatile memory location of the server node. The secondary power supply is to support the data backup process.

Abstract: Example implementations relate to facilitating communication between a memory module and a central processor. In example implementations, a memory module may receive, via a memory bus, a plurality of command strings. The received plurality of command strings may be stored at a reserved set of addresses on the memory module.

Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

Abstract: A test and diagnostics circuit, methods and systems are described. An example test and diagnostics circuit includes a controller and a power monitor coupled to the controller. A load switch on the test and diagnostics circuit selectably implements a load from among multiple load values to test a computing and/or data storage system. The test and diagnostics circuit includes circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the system.

Abstract: Example implementations relate to facilitating communication between a memory module and a central processor. In example implementations, a memory module may receive, via a memory bus, a plurality of command strings. The received plurality of command strings may be stored at a reserved set of addresses on the memory module.

Abstract: According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.

Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

Abstract: A memory module includes memory banks, a local memory controller to access data in the memory banks, and an interface to an external memory controller that is configured to access the memory module. Multiplexing circuitry selectively connects the memory banks to the local memory controller and to the interface to the external memory controller.

Abstract: Booting a computing machine including increasing an operating speed of at least one component of the computing machine during a boot process in response to the computing machine including a sufficient amount of thermal credits and decreasing the operating speed of at least one of the components in response to the computing machine completing the boot process.

Abstract: A computer system includes a memory module. The memory module includes volatile memory, a non-volatile memory subsystem, a host port, and a dual-port buffer device. The dual-port buffer device synchronously couples the non-volatile memory subsystem and the host port to the volatile memory. The dual port buffer device includes routing logic to selectably route address information provided by the host port and the non-volatile memory subsystem to the volatile memory.

Abstract: An apparatus includes a memory module, and the memory module includes a package. The package contains memory dies, and the memory dies share a chip select line.

Abstract: A system includes a hybrid memory module. The hybrid memory module includes volatile memory and non-volatile memory. The system further includes a processor coupled to the hybrid memory module. The processor prevents the hybrid memory module from being mapped during a memory initialization routine by misrepresenting a status of the hybrid memory module.

Abstract: An apparatus includes a hybrid memory module, and the hybrid memory module includes volatile memory and non-volatile memory. Data is prearranged in the volatile memory. The data is committed to the non-volatile memory, as prearranged, in a single write operation when a size of the prearranged data reaches a threshold.

Abstract: A memory module includes memory banks, a local memory controller to access data in the memory banks, and an interface to an external memory controller that is configured to access the memory module. Multiplexing circuitry selectively connects the memory banks to the local memory controller and to the interface to the external memory controller.

Abstract: An electrical jack is disclosed herein. An example of such an electrical jack includes an enclosure configured to define a space in which the electrical plug is inserted. This example also includes an electrostatic discharge assembly positioned in the enclosure and configured to complete a closed circuit with each of the contacts of the electrical plug during insertion within the space, thereby discharging electrostatic energy present on the contacts of the electrical plug. The electrical plug is further configured to present an open circuit to each of the contacts of the electrical plug upon insertion of the electrical plug within the space to a predetermined point. Additional features of this electrical jack are disclosed herein, as are other examples of electrical jacks. An example of an electrical circuit is also disclosed herein.