Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract: A method is provided which includes creating a plasma from a gas mixture including diatomic nitrogen gas and a gas comprising silicon. In addition, the method includes exposing a microelectronic topography to the plasma to form a silicon nitride layer thereon. In some cases, the method may include forming the silicon nitride layer at a temperature less than approximately 300° C. Furthermore, the method may include subsequently processing the microelectronic topography at a temperature greater than or equal to approximately 250° C. such that a stress change of less than approximately 1.0×1010 dynes/cm2 occurs within the silicon nitride layer. In addition, a microelectronic topography is provided which has a silicon nitride layer with a concentration of diatomic hydrogen that is at least one order of magnitude lower than a concentration of diatomic hydrogen within a silicon nitride layer formed from a plasma generated from ammonia.