Patents by Inventor William C. Leipold
William C. Leipold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6823496Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: GrantFiled: April 23, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Publication number: 20040221250Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: ApplicationFiled: June 18, 2004Publication date: November 4, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Publication number: 20040139417Abstract: The invention provides a design and an integrated circuit having a substantially uniform density and electrical characteristics between parts of the IC that are angled at 45 degrees relative to one another. In particular, the invention provides fill tiling patterns oriented substantially uniformly to electrical structures of either orthogonal or 45 degree angle orientation.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Robert J. Allen, John M. Cohn, Peter A. Habitz, William C. Leipold, Ivan L. Wemple, Paul S. Zuchowski
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Patent number: 6760901Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.Type: GrantFiled: April 11, 2002Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Eric M. Coker, William C. Leipold
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Patent number: 6704695Abstract: A method and structure for creating a photomask data set includes inputting a design data set, creating a simulated printed data set by applying a lithography simulation model to chosen levels of the design data set, merging each chosen level of the design data set with each corresponding level of the simulated printed data set in order to produce a merged design data set, applying at least one test to the merged design data set, correcting the design data set based on results of the test to produce a corrected design data set, repeating the creating of the simulated printed data, merging, applying the test and correcting using the corrected design data set until the corrected design data set passes the test, and outputting the corrected design data set as the photomask data set.Type: GrantFiled: July 16, 1999Date of Patent: March 9, 2004Assignee: International Business Machines CorporationInventors: Orest Bula, Daniel C. Cole, Edward W. Conrad, William C. Leipold
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Patent number: 6667136Abstract: A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.Type: GrantFiled: July 22, 2002Date of Patent: December 23, 2003Assignee: International Business Machines CorporationInventors: Orest Bula, Daniel C. Cole, Edward W. Conrad, William C. Leipold
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Patent number: 6662350Abstract: A method and system for generating a set of FinFET shapes. The method and system locate a gate in an FET layout. The set of FinFET shapes is generated coincident with the gate. The method and system can further create a FinFET layout by modifying the FET layout to include the set of FinFET shapes.Type: GrantFiled: January 28, 2002Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: David M. Fried, William C. Leipold, Edward J. Nowak
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Publication number: 20030200513Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: ApplicationFiled: April 23, 2002Publication date: October 23, 2003Applicant: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox
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Publication number: 20030196178Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.Type: ApplicationFiled: April 11, 2002Publication date: October 16, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bette L. Bergman Reuter, Eric M. Coker, William C. Leipold
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Publication number: 20030161525Abstract: An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.Type: ApplicationFiled: February 21, 2002Publication date: August 28, 2003Applicant: International Business Machines CorporationInventors: James A. Bruce, Orest Bula, Edward W. Conrad, William C. Leipold, Michael S. Hibbs, Joshua J. Krueger
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Publication number: 20030145299Abstract: A method and system for generating a set of FinFET shapes. The method and system locate a gate in an FET layout. The set of FinFET shapes is generated coincident with the gate. The method and system can further create a FinFET layout by modifying the FET layout to include the set of FinFET shapes.Type: ApplicationFiled: January 28, 2002Publication date: July 31, 2003Inventors: David M. Fried, William C. Leipold, Edward J. Nowak
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Publication number: 20030080435Abstract: An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.Type: ApplicationFiled: November 26, 2002Publication date: May 1, 2003Inventors: Timothy G. Dunham, Ezra D. B. Hall, Howard S. Landis, Mark A. Lavin, William C. Leipold
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Patent number: 6539321Abstract: Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.Type: GrantFiled: July 17, 2001Date of Patent: March 25, 2003Assignee: International Business Machines CorporationInventors: James A. Bruce, Orest Bula, Edward W. Conrad, William C. Leipold
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Patent number: 6528883Abstract: An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.Type: GrantFiled: September 26, 2000Date of Patent: March 4, 2003Assignee: International Business Machines CorporationInventors: Timothy G. Dunham, Ezra D. B. Hall, Howard S. Landis, Mark A. Lavin, William C. Leipold
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Publication number: 20030018443Abstract: Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, as to the manner in which topography will affect the resist and/or antireflective coating (ARC) thicknesses, so as to improve upon linewidth (LW) control and, in general, imparting improved processing windows. The method can be implemented in the form of computer-executable instructions which are embodied in one or more program modules stored on computer-usable media.Type: ApplicationFiled: July 17, 2001Publication date: January 23, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James A. Bruce, Orest Bula, Edward W. Conrad, William C. Leipold
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Publication number: 20030008220Abstract: A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.Type: ApplicationFiled: July 22, 2002Publication date: January 9, 2003Inventors: Orest Bula, Daniel C. Cole, Edward W. Conrad, William C. Leipold
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Patent number: 6458493Abstract: A method and structure for a photomask that includes a substrate having a first transmittance, a first pattern to be transferred to a photosensitive layer (the first pattern having a second transmittance lower than the first transmittance) and a second pattern having a third transmittance greater than the second transmittance and less than the first transmittance. The second pattern is adjacent at least a portion of the first pattern, and the substrate and the second pattern transmit light substantially in phase.Type: GrantFiled: June 4, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: Orest Bula, Daniel C. Cole, Edward W. Conrad, William C. Leipold
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Patent number: 6429469Abstract: A structure for a semiconductor chip which includes a first region having first cells for storing and processing data, and a second region outside the first region having OPC structures, wherein the OPC structures comprise decoupling capacitors. The line widths of the active gates of first cells are the same size or similar in size as the OPC structures. The OPC structures reduce proximity effects of active devices in the first cells, and comprise N-type FETs and P-type FETs, that are located in the second region. The OPC structures may have a width greater than the first cells. The second region can be multiple OPC structures, whereby the second region comprises multiple decoupling capacitors. The active devices in the first cells are separated by a first distance and the OPC structures are separated from the active devices by the first distance.Type: GrantFiled: November 2, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Archibald J. Allen, Orest Bula, John M. Cohn, Daniel Cole, Edward W. Conrad, William C. Leipold
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Patent number: 6425112Abstract: A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automatically altering the working design data set when the comparing indicates a design rule violation. The method further automatically repeats the creating, the comparing and the automatically altering until no design rule violations occur or no solution to the errors exists.Type: GrantFiled: June 17, 1999Date of Patent: July 23, 2002Assignee: International Business Machines CorporationInventors: Orest Bula, Daniel C. Cole, Edward W. Conrad, William C. Leipold
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Patent number: 6395438Abstract: A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent design features. Adjusted or corrected design data is produced which may be used to create a mask which includes etch bias corrections for better fidelity and reproduction of the original design in the etching step. Etch bias corrections may also be applied based upon characteristics of regions defined in the design, or on a pattern density of the design.Type: GrantFiled: January 8, 2001Date of Patent: May 28, 2002Assignee: International Business Machines CorporationInventors: James A. Bruce, Orest Bula, Edward W. Conrad, William C. Leipold