Patents by Inventor William C. Lindsay

William C. Lindsay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6948096
    Abstract: A functional random instruction testing (FRIT) method is provided for testing complex devices.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: September 20, 2005
    Assignee: Intel Corporation
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay
  • Patent number: 6928638
    Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay, Kamalnayan Jayaraman, Geliang Zhou
  • Publication number: 20030066003
    Abstract: A functional random instruction testing (FRIT) method is provided for testing complex devices.
    Type: Application
    Filed: July 31, 2001
    Publication date: April 3, 2003
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay
  • Publication number: 20030033558
    Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).
    Type: Application
    Filed: August 7, 2001
    Publication date: February 13, 2003
    Inventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay, Kamalnayan Jayaraman, Geliang Zhou