Patents by Inventor William C. Loftin

William C. Loftin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit having a top side wafer contact and a method of manufacture therefor
    Patent number: 7741205
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1810) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: June 22, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Tony Thanh Phan, William C Loftin, John Lin, Philip L Hower
  • Integrated Circuit Having a Top Side Wafer Contact and a Method of Manufacture Therefor
    Publication number: 20080132066
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
    Type: Application
    Filed: January 18, 2008
    Publication date: June 5, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tony T. Phan, William C. Loftin, John Lin, Philip L. Hower
  • Integrated circuit having a top side wafer contact and a method of manufacture therefor
    Patent number: 7345343
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Tony T. Phan, William C. Loftin, John Lin, Philip L. Hower
  • Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor
    Patent number: 7262109
    Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: August 28, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John Lin, Tony T. Phan, Philip L. Hower, William C. Loftin, Martin B. Mollat
  • Diode having a double implanted guard ring
    Patent number: 6894318
    Abstract: The present invention provides a diode 200 that includes a substrate 215 doped with a first type dopant and a double implanted guard ring 245 located within the substrate and doped with a second type dopant opposite the first type dopant and having a first doped profile region 245a and a second doped profile region 245b. The present invention also includes a method of manufacturing this diode and an integrated circuit that utilizes this diode 200 within a CMOS and bipolar transistor integrated circuit 600.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: May 17, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Ming-Yeh Chuang, William C. Loftin, Scott K. Montgomery