Abstract: GaAs FETs exhibit excellent long-term stability if they have a drain ledge, a drain contact with reduced dendrite size, and a silicon nitride passivation layer. Accelerated aging tests at device case temperatures of 250 degrees C. indicate essentially no device failures after 200 hours of observation and a median failure time of approximately 500 hours.

Abstract: The stability of semiconductor devices such as gallium arsenide field effect transistors are significantly improved by controlling the process leading to the production of the drain contact. The process requires that the annealing of metals used to form the contact to gallium arsenide is done under conditions which prevent the excessive formation of metal dendrites penetrating into the gallium arsenide active region.

Abstract: Power handling capability and gain of metal-semiconductor field effect devices is adversely affected by a phenomenon variously known as gate-drain avalanche or gate breakdown which occurs at elevated gate-drain voltage. Consequently, it is desirable to design devices so as to maximize gate-drain breakdown voltage V.sub.gd consistent with maximum output power capability.According to the invention, such voltage is maximized by a gate-drain configuration which involves approximate equalization of per-unit-area mobile charge in a portion of the active layer under the gate contact and in an adjoining portion between gate and drain contacts. Equalization of charge may be achieved by appropriate doping or appropriate choice of layer thickness, either alone or in combination. In particular, if dopant concentration per unit volume is essentially equal in the two portions, approximate equalization of conducting channel thickness in the two portions is called for.

Abstract: Disclosed are unipolar semiconductor devices such as, e.g., metal-semiconductor field effect transistors. The disclosed devices comprise an n- or p-type active layer on a substrate and a drain contact on the active layer.The active layer comprises two contiguous regions, namely a first, more heavily doped region which is in contact with the drain contact and a second, less heavily doped region which in a direction perpendicular to the active layer extends through the remainder of the active layer. In the disclosed configuration the more heavily doped region extends past the edge of the drain contact towards a source of free carriers such as e.g., a source contact.Devices incorporating such configuration of regions in the active layer are more resistant to burnout and are capable of operating at higher voltage and power levels.

Abstract: A nonalloyed ohmic contact (110-112, 120-122) to an n-type Group III(a)-V(a) compound semiconductor body (102-104) is formed by epitaxially growing a Group III(a)-V(a) n.sup.++ -layer (106-108, 106'-108') doped to at least 10.sup.19 cm.sup.-3 between the semiconductor body and a metal contact layer (110-112). The metal layer forms an ohmic contact without requiring heating above the eutectic temperature. In order to avoid contamination of the metal-semiconductor interface, a metal contact layer (120-122) may be deposited in situ after MBE growth of the n.sup.++ -layer. This technique results in both a metal-semiconductor interface with smoother morphology and also an ohmic contact without heating above the eutectic temperature. These procedures are specifically described with reference to the fabrication of GaAs FETs.