Abstract: An IEEE 488 interface couples a microprocessor to one or more devices that are connected to an IEEE 488 bus. Message transmission speed is improved by overlapping a portion of the T1 bus settling time with the microprocessor's write pulse, when it is known that the data on the microprocessor's bus is valid for a predefined period of time before the write pulse's trailing edge. Improved handshake synchronization is achieved by generating an interrupt signal to notify the microprocessor that the last byte of an incoming message has been received. The terminal count signal generated by the microprocessor's DMA controller is used to detect the end of multiple byte messages sent by the microprocessor. The interface automatically generates an EOI signal on the IEEE 488 bus when the last byte of the message is asserted on the IEEE 488 bus data lines. This greatly simplifies the transmission of multiple byte messages by the microprocessor compared with the protocol used by prior art interfaces.

Abstract: A modified IEEE 488.1 bus interface increases, by as much as a factor of eight, the rate at which inter-instrument data transfers can be performed. The bus interface state machines presented in the ANSI/IEEE Std 488.1-1987 have been modified so that if all the devices involved in a particular data transfer are equipped to handle high speed data transfers, then a modified data transmission methodology is used so as to enable multiline messages to be transmitted at a higher speed than would otherwise be possible. If any of the devices involved in a particular data transfer does not have an interface equipped to handle high speed data transfers, this condition is automatically detected by the interfaces with high speed capability, and then the standard data transmission methodology is used. The high speed data transmission mode is totally transparent to the controller software in that it does not require any changes to the controller software nor to the device drivers and device application programs.

Abstract: An IEEE 488 interface couples a microprocessor to one or more devices that are connected to an IEEE 488 bus. Message transmission speed is improved by overlapping a portion of the T1 bus settling time with the microprocessor's write pulse, when it is known that the data on the microprocessor's bus is valid for a predefined period of time before the write pulse's trailing edge. Improved handshake synchronization is achieved by generating an interrupt signal to notify the microprocessor that the last byte of an incoming message has been received. The terminal count signal generated by the microprocessor's DMA controller is used to detect the end of multiple byte messages sent by the microprocessor. The interface automatically generates an EOI signal on the IEEE 488 bus when the last byte of the message is asserted on the IEEE 488 bus data lines. This greatly simplifies the transmission of multiple byte messages by the microprocessor compared with the protocol used by prior art interfaces.