Abstract: A method of and container for temperature-controlled meal transport are provided. A food tray accommodation area is defined in the interior of the meal transport container. A plurality of ledges are defined in the food tray accommodation area, the ledges designed to support a plurality of different sized food trays. An insulator is provided to insulate the food tray accommodation area. A pair of integral upper carrying handles and a pair of integral lower handles are provided. The upper integral carrying handles are designed to nest with the integral lower handles when a plurality of meal transport containers are stacked. A thermometer monitors temperature within the food tray accommodation area. Heating elements heat cooked food from a cooled temperature to an appropriate hot-serving temperature, maintain heated food at temperature, and cook raw food.

Abstract: In accordance with the principals of the present invention, a computer-controlled valve array to meter fluids is provided. An intake manifold defines a fluid-inlet chamber. A fluid inlet is in fluid communication with the fluid-inlet chamber of the intake manifold, the fluid inlet adapted to receive a high-pressure source of fluid. A number of valves have an inlet and an outlet. In an embodiment, the valves comprise pintle valves. At least one valve inlet is in fluid communication with the fluid-inlet chamber. The valves are electronically controlled to allow fluid through in response to a trigger. An outtake manifold is in fluid communication with the valve outlets. Outlet ports are in fluid communication with the outtake chamber of the outlet manifold. The outlet ports are adapted to receive and fluid communicate with the output circuit.

Abstract: A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.

Abstract: A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or are not exclusively relied on by the processor-cache to assure validity of the data in the cache (e.g., a 386-bus compatible computer system using an external secondary cache in which bus arbitration signals are only connected to and used by the secondary cache controller). In an exemplary external-chip implementation, the cache coherency system (120) comprises two PLAs--a FLUSH module (122) and a WAVESHAPING module (124). The FLUSH module (a) receives selected bus cycle definition and control signals from a microprocessor ((110), (b) detects FLUSH (cache invalidation) conditions, i.e., bus master synchronization events, and for each such FLUSH condition, (c) provides a FLUSH output signal.