Patents by Inventor William C. Rash
William C. Rash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10235175Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.Type: GrantFiled: April 4, 2016Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
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Patent number: 10073513Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.Type: GrantFiled: April 20, 2016Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
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Patent number: 9703562Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.Type: GrantFiled: March 16, 2013Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: William C. Rash, Bret L. Toll, Scott D. Hahn, Glenn J. Hinton
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Publication number: 20160342196Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.Type: ApplicationFiled: April 20, 2016Publication date: November 24, 2016Inventors: WILLIAM C. RASH, MARTIN G. DIXON, YAZMIN A. SANTIAGO
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Publication number: 20160216967Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Applicant: Intel CorporationInventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
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Patent number: 9395990Abstract: A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates a memory location of a memory as a source operand and indicates a register as a destination operand. The method includes loading data from the indicated memory location to the processor in response to the partial width load instruction. The method includes writing at least a portion of the loaded data to a partial width of the register in response to the partial width load instruction. The method includes finishing writing the register with a set of bits stored in a remaining width of the register that have bit values that depend on a partial width load mode of the processor. The partial width load instruction does not indicate the partial width load mode. Other methods, processors, and systems are also disclosed.Type: GrantFiled: June 28, 2013Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: William C. Rash, Yazmin A. Santiago, Martin Guy Dixon
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Patent number: 9354681Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.Type: GrantFiled: June 28, 2013Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
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Patent number: 9323535Abstract: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction. The activation instruction is to occur before the enforcement instruction in a program order. The processor also includes an instruction order enforcement module. The instruction order enforcement module, in response to the pair of the instruction order enforcement instructions, is to prevent instructions occurring after the enforcement instruction in the program order, from being processed prior to the activation instruction, in an out-of-order portion of the processor. Other processors are also disclosed, as are various methods, systems, and instructions.Type: GrantFiled: June 28, 2013Date of Patent: April 26, 2016Assignee: Intel CorporationInventors: Martin Guy Dixon, William C. Rash, Yazmin A. Santiago
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Patent number: 9304940Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.Type: GrantFiled: March 15, 2013Date of Patent: April 5, 2016Assignee: Intel CorporationInventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
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Patent number: 9202056Abstract: Embodiments of an invention for inter-processor attestation hardware are disclosed. In one embodiment, an apparatus includes first attestation hardware associated with a first portion of a system. The first attestation hardware is to attest to a second portion of the system that the first portion of the system is secure.Type: GrantFiled: March 15, 2013Date of Patent: December 1, 2015Assignee: Intel CorporationInventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
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Publication number: 20150006851Abstract: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction. The activation instruction is to occur before the enforcement instruction in a program order. The processor also includes an instruction order enforcement module. The instruction order enforcement module, in response to the pair of the instruction order enforcement instructions, is to prevent instructions occurring after the enforcement instruction in the program order, from being processed prior to the activation instruction, in an out-of-order portion of the processor. Other processors are also disclosed, as are various methods, systems, and instructions.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Martin Guy Dixon, William C. Rash, Yazmin A. Santiago
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Publication number: 20150006856Abstract: A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates a memory location of a memory as a source operand and indicates a register as a destination operand. The method includes loading data from the indicated memory location to the processor in response to the partial width load instruction. The method includes writing at least a portion of the loaded data to a partial width of the register in response to the partial width load instruction. The method includes finishing writing the register with a set of bits stored in a remaining width of the register that have bit values that depend on a partial width load mode of the processor. The partial width load instruction does not indicate the partial width load mode. Other methods, processors, and systems are also disclosed.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: William C. RASH, Yazmin A. SANTIAGO, Martin Guy DIXON
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Publication number: 20150006917Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
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Publication number: 20140283032Abstract: Embodiments of an invention for inter-processor attestation hardware are disclosed. In one embodiment, an apparatus includes first attestation hardware associated with a first portion of a system. The first attestation hardware is to attest to a second portion of the system that the first portion of the system is secure.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
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Publication number: 20140281196Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
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Publication number: 20140281236Abstract: Systems and methods for implementing transactional memory access. An example method may comprise initiating a memory access transaction; executing a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, and/or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location; executing a non-transactional read operation with respect to a third memory location, and/or a non-transactional write operation with respect to a fourth memory location; responsive to detecting, by the memory access tracking logic, access by a device other than the processor to the first memory location or the second memory location, aborting the memory access transaction; and completing, irrespectively of the state of the third memory location and the fourth memory location, the memory access transaction responsive to failing to detect a transaction aborting condition.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: William C. Rash, Scott D. Hahn, Bret L. Toll, Glenn J. Hinton
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Publication number: 20140281399Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.Type: ApplicationFiled: March 16, 2013Publication date: September 18, 2014Inventors: WILLIAM C. RASH, BRET L. TOLL, SCOTT D. HAHN, GLENN J. HINTON
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Publication number: 20140281398Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.Type: ApplicationFiled: March 16, 2013Publication date: September 18, 2014Inventors: WILLIAM C. RASH, Martin G. Dixon, Yazmin A. Santiago