Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: The invention provides methods and apparatus for improving the direct current (DC) offset performance of an oversampling analog-to-digital (A/D) converter, including A/D converters that include an oversampling quantizer such as a single or multi-bit &Dgr;-&Sgr; modulator, successive approximation quantizer, flash quantizer, pipelined quantizer or other suitable oversampling quantizer. The invention also relates to methods for providing a wide-band attenuation in the digital output of an A/D converter using a limited number of components.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: A signal processor circuit which receives an input signal and two control words and is programmable to vary the level and the output voltage range of the output signal is provided. The signal processor includes a converter circuit and a level circuit which provide the output circuit with intermediate signals based on input control signals, e.g., input digital words. The output circuit receives an additional control signal and the intermediate signals and is programmable to modify the output voltage range and level of the output signal based on the additional control signal, e.g., a digital word.

Abstract: A switch impedance insensitive signal processor is provided. A signal processor according to the present invention overcomes the problem of switch impedance by adding an individual buffer, e.g. a unity-gain amplifier, between the switch and the processor portion of the circuit. The buffer isolates the signal processor from the switch impedance.

Abstract: An oversampling data converter with good rejection capability is provided. The oversampling data converter includes three primary parts; a delta-sigma modulator for sampling and digitizing incoming analog signals, a high order digital filter for discarding unwanted frequency components, and an internal clock generator for controlling the operation of the modulator and the filter. All three primary parts are provided in the same package and also on the same die. No frequency-setting external components are necessary. The high order digital filter provides more than 100 dB rejection at a first null frequency. The first null provided by the filter has a sufficiently broad range so as to allow a low accuracy internal clock generator to be used. If necessary, the clock can be generated externally or from some other part of the system.

Abstract: A simple, low-cost circuit and method for line zing parasitic capacitances of transistor junctions, independent of the process technology employed, are provided. In the preferred embodiment, the parasitic capacitance of a transistor in a track and hold circuit is linearized by providing a pair of diodes that act inversely to the parasitic diodes formed within the integrated circuit during normal tracking operations. Without the diodes of the present invention, the varying input signals cause the parasitic capacitance to vary, thereby causing harmonic distortion in the track and hold circuit. An alternate embodiment of the present invention is also provided in which a second complementary transistor is provided. The inclusion of the complementary transistor results in a second set of parasitic capacitances that are substantially opposite the parasitic capacitances of the track and hold transistor.

Abstract: Serial analog-to-digital converters (ADC) in which power down and power up modes are activated by two dual-purpose input signals are provided. The ADCs of the invention eliminate the need for a dedicated power down input line as found on typical serial ADCs. When commanded to do so, the ADC enters into one of two power down modes, NAP or SLEEP. In NAP mode, only those portions of the ADC circuit which consume current and which are capable of waking up almost instantaneously are powered down. In SLEEP mode, the entire ADC circuit is powered down. When commanded to do so, the ADC enters into a power up mode, applying current to every portion of the ADC circuit. Wake-up from the NAP mode takes place almost instantaneously. Wake-up from the SLEEP mode requires additional time. From either mode, a signal is generated when the ADC conversion circuit, which preferably includes a reference voltage generator, has stabilized sufficiently for the ADC to perform analog-to-digital conversion.

Abstract: A segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies.

Abstract: Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.

Abstract: An electrostatic discharge protection clamp particularly useful for with bipolar and biCMOS integrated circuits include an NPN transistor formed in an isolated tub in an epitaxial layer grown on a substrate. The collector of the NPN transistor is connected to the input terminal, and the emitter of the NPN transistor is connected to the substrate. A resistor interconnects the base and the emitter. Advantageously, the P-doped base can abut the P-doped isolation region forming the tub, and the P-doped isolation region can interconnect the emitter to the substrate. Below BV.sub.CES the clamp will look like an open circuit, and above BV.sub.CES the transistor will start conducting current. The transistor will break down collector to base. Conduction of the transistor causes a voltage drop across the base-emitter junction, and when this voltage drop exceeds the base-emitter forward voltage the transistor will turn on.

Abstract: A constant current amplifier stage for a voltage comparator circuit includes a first CMOS transistor pair having a common gate terminal and a common drain terminal and a second CMOS transistor pair which functions as a load for the first CMOS transistor pair. The second CMOS transistor pair has a common gate terminal and a common drain terminal both of which are connected to the common drain terminal of the first CMOS transistor pair. The transistors are configured so that the current through the first transistor pair at null is at least twice the current through the second transistor pair at null voltage.

Abstract: A bidirectional shift register includes a plurality of serially connected cells with each cell having a first circuit portion and a second circuit portion. Each circuit portion includes at least two parallel inverters connected in opposite directions. The relative transconductance of the oppositely connected inverters in each circuit portion of a cell can be varied thereby determining the direction of data flow through the circuit portion and through the bidirectional shift register.