Abstract: A real time, on-the-fly data encryption system is operable to encrypt and decrypt data flow between a secure processor and an unsecure external memory systen. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

Abstract: A method includes transferring, by a memory controller from non-volatile memory to volatile memory, a bit sequence comprising video data and control information and transferring, by a first programmable real-time unit (PRU) from the volatile memory to a scratchpad register, the bit sequence. The method also includes transferring, by a second PRU from the scratchpad register to a general purpose input output (GPIO) register, the bit sequence, where the GPIO register is adapted to be coupled to a spatial light modulator (SLM).

Abstract: A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

Abstract: A system for detecting tamper events in a digital circuit by having a Critical Path Replica (CPR) circuit operable in parallel with the circuit being monitored, and adjusted to generate a timing violation if the operating parameters of the circuit change to be outside the normal operating parameters. The critical path replica circuit is adjusted to generate a timing violation before the actual circuit being monitored fails due to the changed operating parameters.

Abstract: A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with it's own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.

Abstract: A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. A Message Authentication Code is also employed to detect any memory corruption or unauthorized memory modification.

Abstract: A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with it's own separate encryption capability, or no encryption at all. Speculative decryption operations may be started when the memory used is capable of returning read data out of order. The full or partial results of the speculative operations are cached in order to allow matching the cryptographic operation to the read data when it arrives.

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract: This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance.

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract: A system for detecting tamper events in a digital circuit by having a Critical Path Replica (CPR) circuit operable in parallel with the circuit being monitored, and adjusted to generate a timing violation if the operating parameters of the circuit change to be outside the normal operating parameters. The critical path replica circuit is adjusted to generate a timing violation before the actual circuit being monitored fails due to the changed operating parameters.

Abstract: A random number generator circuit for generating a sequence of random numbers. A linear feedback shift register includes shift register circuitry that holds a plurality of shift register bits. The shift register circuitry shifts the shift register bits responsive to a periodic system clock signal, shifting out one of the shift register bits while shifting in a feedback bit whose value is provided at a feedback input of the shift register. Tap circuitry generates the feedback bit by logically combining selected ones of the shift register bits. Sampling circuitry provides at least a portion of the shift register bits as one of the sequence of random numbers. Interface circuitry provides a random number from the shift register, to a processor via a processor bus, in response to a processor request signal being asserted.