Patents by Inventor William C. Wille
William C. Wille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7838390Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: GrantFiled: October 12, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Patent number: 7635899Abstract: A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.Type: GrantFiled: January 11, 2007Date of Patent: December 22, 2009Assignee: International Business Machines CorporationInventors: Haining S. Yang, Thomas W. Dyer, William C. Wille
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Patent number: 7550364Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.Type: GrantFiled: January 30, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, William K. Henson, Kern Rim, William C. Wille
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Publication number: 20090098706Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Publication number: 20090047791Abstract: A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David M. Dobuzinsky, Johnathan E. Faltermeier, Munir D. Naeem, William C. Wille, Richard S. Wise
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Publication number: 20080171420Abstract: A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Haining S. Yang, Thomas W. Dyer, William C. Wille
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Publication number: 20070293016Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.Type: ApplicationFiled: June 14, 2006Publication date: December 20, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Phung T. Nguyen, William C. Wille, Richard Lindsay, Zhao Lun, Yung Fu Chong, Siddhartha Panda
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Publication number: 20070267671Abstract: A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lisa F. Edge, Johnathan E. Faltermeier, Paul C. Parries, William C. Wille
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Patent number: 7202513Abstract: A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.Type: GrantFiled: September 29, 2005Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, William K. Henson, Kern Rim, William C. Wille
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Patent number: 7183130Abstract: A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.Type: GrantFiled: July 29, 2003Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Joachim Nuetzel, Xian Jay Ning, William C. Wille
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Patent number: 7030031Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.Type: GrantFiled: June 24, 2003Date of Patent: April 18, 2006Assignee: International Business Machines CorporationInventors: William C. Wille, Daniel C. Edelstein, William J. Cote, Peter E. Biolsi, John Fritche, Allan W. Upham
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Publication number: 20040266201Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.Type: ApplicationFiled: June 24, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William C. Wille, Daniel C. Edelstein, William J. Cote, Peter E. Biolsi, John E. Fritche, Allan W. Upham
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Patent number: 6762667Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.Type: GrantFiled: June 19, 2003Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca, Kenneth J. Stein, William C. Wille
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Publication number: 20030210124Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.Type: ApplicationFiled: June 19, 2003Publication date: November 13, 2003Inventors: Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca, Kenneth J. Stein, William C. Wille
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Patent number: 6621392Abstract: A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.Type: GrantFiled: April 25, 2002Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca, Kenneth J. Stein, William C. Wille
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Patent number: 6593617Abstract: Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.Type: GrantFiled: February 19, 1998Date of Patent: July 15, 2003Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur, William C. Wille
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Patent number: 6461529Abstract: A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas.Type: GrantFiled: April 26, 1999Date of Patent: October 8, 2002Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Waldemar W. Kocon, William C. Wille, Richard Wise
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Patent number: 6207353Abstract: A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer.Type: GrantFiled: December 10, 1997Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: Michael D. Armacost, Willard E. Conley, Tina J. Cotler-Wagner, Ronald A. DellaGuardia, David M. Dobuzinsky, Michael L. Passow, William C. Wille
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Patent number: 6143635Abstract: Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor.Type: GrantFiled: August 16, 1999Date of Patent: November 7, 2000Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur, William C. Wille
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Patent number: 6093281Abstract: A baffle plate for semiconductor processing apparatus. The baffle plate includes a plurality of slits. A plurality of fins are located between adjacent slits. The fins have varying heights and a supporting portion interconnects the fins.Type: GrantFiled: February 26, 1998Date of Patent: July 25, 2000Assignee: International Business Machines Corp.Inventors: Richard S. Wise, David M. Dobuzinsky, William C. Wille