Patents by Inventor William Clark Naylor, Jr.
William Clark Naylor, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10650109Abstract: Techniques and systems for solving a Boolean satisfiability (SAT) problem are described. Specifically, embodiments solve the SAT problem by generating an extended resolution proof. It is well-known that many technological problems can be modeled as SAT problems, and that solving an underlying SAT problem effectively solves the original technological problem. Therefore, embodiments described herein can be used to solve any technological problem that can be modeled as a SAT problem.Type: GrantFiled: January 31, 2019Date of Patent: May 12, 2020Assignee: Synopsys, Inc.Inventor: William Clark Naylor, Jr.
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Patent number: 10346578Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.Type: GrantFiled: November 1, 2017Date of Patent: July 9, 2019Assignee: Synopsys, Inc.Inventors: Jagat B. Patel, William Clark Naylor, Jr., Brent L. Gregory
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Patent number: 10331834Abstract: A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.Type: GrantFiled: June 22, 2017Date of Patent: June 25, 2019Assignee: Synopsys, Inc.Inventors: Bogdan Craciun, Brent Gregory, Jaime Wong, William Clark Naylor, Jr.
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Publication number: 20180121591Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.Type: ApplicationFiled: November 1, 2017Publication date: May 3, 2018Applicant: Synopsys, Inc.Inventors: Jagat B. Patel, William Clark Naylor, JR., Brent L. Gregory
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Publication number: 20180004862Abstract: A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.Type: ApplicationFiled: June 22, 2017Publication date: January 4, 2018Applicant: Synopsys, Inc.Inventors: Bogdan Craciun, Brent Gregory, Jaime Wong, William Clark Naylor, JR.
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Patent number: 6951003Abstract: A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective function. The grouping produce a plurality of cell clusters. The model formed may be a binary tree. The curvature of the objective function for each of the cell clusters is estimated. Interactions between said cell clusters are described as a relation. A set of preconditioning values which achieves a separation of variables of the relation is determined. The preconditioning may be applied to a conjugate gradient placement process to advantageously decrease the number of iterations required to produce an optimized placement of the cells.Type: GrantFiled: May 12, 2003Date of Patent: September 27, 2005Assignee: Synopsys, IncInventors: Troy W. Barbee, III, William Clark Naylor, Jr., Ross Alexander Donelly
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Patent number: 6384836Abstract: A process of displaying images on output displays, incompatible with the input format, is disclosed. In particular, a process of displaying RGB input on a screen having Red, Green, Blue and White bi-level pixel elements defines a convex hull of the output points and maps the input data into the convex hull. Those values are moved outside the convex hull so that they lie on the surface of the convex hull and the mapped values are halftoned to produce output pixel elements corresponding to an approximation of the input pixels.Type: GrantFiled: August 27, 1997Date of Patent: May 7, 2002Assignee: Canon Inc.Inventors: William Clark Naylor, Jr., Kia Silverbrook
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Patent number: 5987219Abstract: A dither matrix is produced by creating an array of dots and dividing the array into a mutiplicity of regions, each of the regions having a multiplicity of dots. Borders of the regions are altered to have substantially continuous randomly irregular boundaries, and dither values are assigned to each of the regions.Type: GrantFiled: May 28, 1996Date of Patent: November 16, 1999Assignee: Canon Information Systems Research Australia Pty. Ltd.Inventors: William Clark Naylor, Jr., Kia Silverbrook
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Patent number: 5844532Abstract: A color display system that is capable of taking input intended to be displayed on a full color display (e.g. VDU) having a high refresh rate and displaying the image on a display having a much reduced number of displayable colors and a lower refresh rate. 24-bit RGB data is input and converted into bi-level RGBW data and halftoned in a render unit for storage before display. Motion detection is used to ensure that only those pixels that have change in value are updated on the display.Type: GrantFiled: January 5, 1996Date of Patent: December 1, 1998Assignee: Canon Inc.Inventors: Kia Silverbrook, William Clark Naylor, Jr., Michael Webb, David Ross Brown, Natalie Lisa Kershaw, Mark Pulver, Rodney James Whitby
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Patent number: 5805136Abstract: The design of a single pixel in a discrete level display is replicated a large number of times, often over a million times. The design of the pixel arrangement has substantial consequences in the quality of any image reproduced utilizing the pixel arrangement. In reducing unwanted artifacts, many factors must be considered. The present invention discloses a superior form of pixel arrangement for a discrete level display having optically balanced properties in addition to an intermingling of illumination areas at higher intensities and an irregular format of illumination.Type: GrantFiled: June 20, 1997Date of Patent: September 8, 1998Assignee: Canon Kabushiki KaishaInventors: Kia Silverbrook, William Clark Naylor, Jr.
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Patent number: 5801854Abstract: A method of displaying color images, intended to be displayed on a first color display device, on a second color display device having a color gamut (2) different from a color gamut (1) of the first color display device. The method includes a first step of determining a plurality of input extrema color values (RGB), within the color gamut (1) of the first color display device and at the extrema of the gamut of the first color display. Next, the method determines a plurality of output extrema color values (R'G'B') corresponding to the input extrema color values (RGB), within the color gamut (2) of the second color display and at the extrema of the gamut (2) of the second color display.Type: GrantFiled: February 12, 1996Date of Patent: September 1, 1998Assignee: Canon Information Systems Research Australia Pty LtdInventor: William Clark Naylor, Jr.
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Patent number: 5757516Abstract: An apparatus and method for suppressing noise and an input image having a plurality of pixels, each of the pixels in the plurality of pixels having a range of possible values between at least two extremities. A first group of pixels is determined, each pixel of the first group having a value that is less than a predetermined amount from the value of at least one of the extremities. The values of pixels adjacent to each pixel in the first group are examined to determine if the adjacent pixels are also members of the first group and, when a predetermined number of the pixels adjacent to a pixel in the first group are also members of the first group, reassigning the pixel value of that pixel in the first group and each of its adjacent pixels to have the value of at least one of the extremities.Type: GrantFiled: January 4, 1994Date of Patent: May 26, 1998Assignee: Canon Inc.Inventor: William Clark Naylor, Jr.
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Patent number: 5751272Abstract: A pixel display includes a pixel pattern containing multiple pixels each of which having multiple primary color sub-regions of illumination. These sub-regions are arranged such that they extend in a first direction substantially from one side of the pixel to the other, and in a second direction, substantially normal to the first direction, they have only a limited extent in the pixel. These sub-regions include a multiple number of illumination areas and are arranged such that the center of illumination is substantially stable with respect to movement in the first direction and is substantially constrained to movement in the second direction.Type: GrantFiled: March 13, 1995Date of Patent: May 12, 1998Assignee: Canon Kabushiki KaishaInventors: Kia Silverbrook, William Clark Naylor, Jr.
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Patent number: 5706105Abstract: A method of creating a three dimensional halftone dither matrix, in which the matrix is divided into a predetermined number of levels with each level comprising a two dimensional matrix of activation indicators having positional values including x and y positional components. The method includes the steps of firstly creating a series of three dimensional curves, from a two dimensional array of dither values, the two dimensional array being of the same dimensions as the two dimensional matrix and including level value entries, each of the level value entries having a corresponding three dimensional curve, the three dimensional curve starting at a starting level corresponding to the dither matrix value and at a position corresponding to the x and y positional components of the level value entry, the three dimensional curve terminating at the highest level of the three dimensional halftone dither matrix and taking one x and y positional value on each level between the starting level and the highest level.Type: GrantFiled: August 1, 1995Date of Patent: January 6, 1998Assignee: Canon Kabushiki KaishaInventor: William Clark Naylor, Jr.