Patents by Inventor WILLIAM COLIN WOOD

WILLIAM COLIN WOOD has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Instructions and logic to provide advanced paging capabilities for secure enclave page caches
    Patent number: 9430384
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: March 31, 2013
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Carlos V Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A Goldsmith, Barry E Huntley, Anton Ivanov, Simon P Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott Dion Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H Smith, William Colin Wood
  • INSTRUCTIONS AND LOGIC TO PROVIDE ADVANCED PAGING CAPABILITIES FOR SECURE ENCLAVE PAGE CACHES
    Publication number: 20140297962
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Application
    Filed: March 31, 2013
    Publication date: October 2, 2014
    Inventors: CARLOS V ROZAS, ILYA ALEXANDROVICH, ITTAI ANATI, ALEX BERENZON, MICHAEL A GOLDSMITH, BARRY E HUNTLEY, ANTON IVANOV, SIMON P JOHNSON, REBEKAH M. LESLIE-HURD, FRANCIS X. MCKEEN, GILBERT NEIGER, RINAT RAPPOPORT, SCOTT DION RODGERS, UDAY R. SAVAGAONKAR, VINCENT R. SCARLATA, VEDVYAS SHANBHOGUE, WESLEY H SMITH, WILLIAM COLIN WOOD