Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract: RFID systems, devices, software and methods are adapted for receiving from an RFID tag at least waves that communicate at least a first version of its code. An output tag code is output that is the same as the first version, if a fidelity criterion is met regarding the first version. If not met, the output tag code is instead a final version that is reconstructed from the first version, and also from any additionally optionally subsequently received versions. In some embodiments, an error recovery block includes a subcomponent fidelity criterion checking block that can determine whether the fidelity criterion is met, and a code reconstruction block that can derive the final version.

Abstract: Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Radio frequency identification (RFID) tags are associated with sensors. Sensor data from a sensor is internally associated with a mask address, such as that of a memory. The tags receive commands by a reader, which can include selection commands. The selection commands can be for selecting according to the sensor data, by invoking the mask address. The selection commands can be further associated with a mask value, calling for setting a selection flag only by those tags whose sensor data meets a selection condition relative to the mask value. Therefore the reader can select a sub-population of tags from a larger population based on sensor data.

Abstract: An RFID tag circuit is described having a pair of signal paths that flow to an input of a demodulator of the RFID tag circuit. A first of the signal paths couple the demodulator to an antenna port of the RFID tag circuit. A second of the signal paths couple the demodulator to a location where a pseudo antenna signal first appears on the RFID tag circuit while the RFID tag circuit is being tested on-wafer.

Abstract: An interference canceller for a RFID reader senses a signal related to the interference signal in the receive path of the reader. The canceller outputs an adjustment signal that depends on the sensed signal, which is coupled into the receive path before a downconverter in the receive path. The canceller can use a signal derived from the transmit path in generating the adjustment signal. The canceller adjusts the amplitude or phase (or both) of the derived signal to form the adjustment signal so that it cancels a carrier feed-through interference signal when injected into the receive path. The canceller can include a vector modulator to adjust the amplitude and/or phase of the derived signal; or alternatively, the canceller can include a variable attenuator and a variable phase shifter to adjust the amplitude and/or phase of the derived signal. The loop can be continuous or non-continuous.

Abstract: Systems and methods to determine timebase and timing (i.e., time sync) of received signals in RFID systems. Multiple matched filters corresponding to multiple timebases are used to receive the preambles of signals received from RFID tags. The multiple matched filters define a range of expected timebases of the received signals. The matched filter with the maximum output signal peak is used to derive the timebase and timing of the received signal. Viterbi techniques can be used in determining the timebase and timing to incorporate a portion of the data signal in addition to the preamble. Reconfigurable matched filters can be used so that after a preliminary timebase is determined as described above, the matched filters can be reconfigured to define a new smaller range centered about the preliminary timebase. This allows the timebase to be determined with finer resolution when another preamble portion is received.

Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.

Abstract: Analog-valued floating-gate transistors are used as trimmable circuit components for modifying and/or controlling the gain, phase, offset, frequency response, current consumption, and/or transfer function of signal pathways in parallel and/or serial processing circuits in radio frequency, analog, or mixed-signal integrated circuits.