Abstract: Methods and apparatus for reducing electromagnetic interference resultant from data transmission over a high-speed audio/visual interface. In one embodiment, an HDMI source device is disclosed. The HDMI source device includes a wireless interface and an HDMI interface coupled with an active filter circuit topology. The active filter circuit topology includes a pair of differential signal lanes; a passive filter circuit disposed within each of the pair of differential signal lanes; a plurality of active filter circuits, with at least a first active filter circuit disposed on one side of the passive filter circuit and at least a second active filter circuit disposed on the other side of the passive filter circuit; a plurality of diodes, with each of the plurality of active filter circuits coupled with a respective diode; and switching logic coupled with the plurality of diodes. Methods of operating the HDMI source device and HDMI systems are also disclosed.

Abstract: Methods and apparatus for reducing electromagnetic interference resultant from data transmission over a high-speed audio/visual interface. In one embodiment, an HDMI source device is disclosed. The HDMI source device includes a wireless interface and an HDMI interface coupled with an active filter circuit topology. The active filter circuit topology includes a pair of differential signal lanes; a passive filter circuit disposed within each of the pair of differential signal lanes; a plurality of active filter circuits, with at least a first active filter circuit disposed on one side of the passive filter circuit and at least a second active filter circuit disposed on the other side of the passive filter circuit; a plurality of diodes, with each of the plurality of active filter circuits coupled with a respective diode; and switching logic coupled with the plurality of diodes. Methods of operating the HDMI source device and HDMI systems are also disclosed.

Abstract: Connector inserts and receptacles that provide signal paths having desired impedance characteristics. One example may provide a connector system having a connector insert and a connector receptacle. Contacts in the connector insert may form signal paths with corresponding contacts in the connector receptacle. Additional traces in the connector insert and receptacle may be part of these signal paths. The signal paths may have a target or a desired impedance along their lengths such that the power paths electrically appear as transmission lines. Constraints on physical dimensions of the connector insert and connector receptacle contacts may result in variations in impedance along the signal paths. Accordingly, embodiments of the present invention may provide structures to reduce these variations, to compensate for these variations, or a combination thereof.

Abstract: Connector inserts and receptacles that provide signal paths having desired impedance characteristics. One example may provide a connector system having a connector insert and a connector receptacle. Contacts in the connector insert may form signal paths with corresponding contacts in the connector receptacle. Additional traces in the connector insert and receptacle may be part of these signal paths. The signal paths may have a target or a desired impedance along their lengths such that the power paths electrically appear as transmission lines. Constraints on physical dimensions of the connector insert and connector receptacle contacts may result in variations in impedance along the signal paths. Accordingly, embodiments of the present invention may provide structures to reduce these variations, to compensate for these variations, or a combination thereof.

Abstract: Connector inserts and receptacles that provide signal paths having desired impedance characteristics. One example may provide a connector system having a connector insert and a connector receptacle. Contacts in the connector insert may form signal paths with corresponding contacts in the connector receptacle. Additional traces in the connector insert and receptacle may be part of these signal paths. The signal paths may have a target or a desired impedance along their lengths such that the power paths electrically appear as transmission lines. Constraints on physical dimensions of the connector insert and connector receptacle contacts may result in variations in impedance along the signal paths. Accordingly, embodiments of the present invention may provide structures to reduce these variations, to compensate for these variations, or a combination thereof.

Abstract: Connector inserts and receptacles that provide signal paths having desired impedance characteristics. One example may provide a connector system having a connector insert and a connector receptacle. Contacts in the connector insert may form signal paths with corresponding contacts in the connector receptacle. Additional traces in the connector insert and receptacle may be part of these signal paths. The signal paths may have a target or a desired impedance along their lengths such that the power paths electrically appear as transmission lines. Constraints on physical dimensions of the connector insert and connector receptacle contacts may result in variations in impedance along the signal paths. Accordingly, embodiments of the present invention may provide structures to reduce these variations, to compensate for these variations, or a combination thereof.

Abstract: A high-speed I/O interface that allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages (“VDMs”) for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O (“CIO”) interface. The devices can be designed to provide synchronization (time value, frequency, and phase) among a network of routers, with signal paths of several meters, thereby providing an accurate time base suitable for exacting audiovisual applications.

Abstract: A high-speed optical interface for connecting computers to external I/O devices allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages (“VDMs”) for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O (“CIO”) interface. Standard PCIe bridges are modified to support peer-to-peer communications, allowing greater exploitation of the capabilities of PCIe.

Abstract: A small form-factor, high performance connector is disclosed. This connector is intended for use with high bandwidth digital video, implementing differential digital signaling, as well as for high bandwidth analog video. The described connector system performs the function of the Digital Visual Interface (DVI) connector, but in a significantly smaller package. Signal integrity is maintained in the smaller form factor by the expedient assignment of signals to pins so that the pin above or below any signal is not used on that interface, thus reducing the chances for signal crosstalk. The pin shape and spacing are created to match pin lengths and minimize inductance while maintaining the proper impedance up to 2.5 GHz. This connector system also implements a tactile feedback mechanism to aid with cable plug insertion, and incorporates a keying mechanism to prevent reverse-plugging.

Abstract: A small form-factor, high performance connector is disclosed. This connector is intended for use with high bandwidth digital video, implementing differential digital signaling, as well as for high bandwidth analog video. The described connector system performs the function of the Digital Visual Interface (DVI) connector, but in a significantly smaller package. Signal integrity is maintained in the smaller form factor by the expedient assignment of signals to pins so that the pin above or below any signal is not used on that interface, thus reducing the chances for signal crosstalk. The pin shape and spacing are created to match pin lengths and minimize inductance while maintaining the proper impedance up to 2.5 GHz. This connector system also implements a tactile feedback mechanism to aid with cable plug insertion, and incorporates a keying mechanism to prevent reverse-plugging.

Abstract: Methods and apparatuses for detecting digital signals in high speed signaling systems. In at least one embodiment, at least one received input signal is combined with a plurality of predetermined reference signals according to a plurality of prior digital signal output states to generate a signal for detecting a present digital signal output state. In one aspect of the invention, a method for determining a digital signal state in a differential signaling system includes: comparing a first differential input signal to a second differential input signal; determining a prior digital signal output state; comparing the first differential input signal to one of a first reference voltage and a second reference voltage; comparing the second differential input signal to one of the first reference voltage and the second reference voltage; and determining a present digital signal output state from the prior digital signal output state and from all of the comparisons.

Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: A system that selectively couples one or more IC chips to card slots. The system contains a Z-bar switch which includes: a select input; a first IC port coupled to a first IC pin; a second IC port coupled to a second IC pin; a first card slot port coupled to a first card slot pin; and a second card slot port coupled to a second card slot pin. If the select input receives a first control pattern, the Z-bar switch is configured to: couple the first IC port to the first card slot port; and to couple the second IC port to the second card slot port. If the select input receives a second control pattern, the Z-bar switch is configured to: couple the first IC port to the second card slot port; leave the second IC port floating; and to leave the first card slot port floating.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: A method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains is described. In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. The apparatus also includes a clock signal generator coupled to the first subsystem and coupled to the second subsystem. The clock signal generator is to supply a first clock to the first subsystem and to supply a second clock to the first subsystem and to supply a third clock to the second subsystem. Each of the first clock, the second clock and the third clock are derived from a common clock, the first clock having a first predetermined phase offset relative to the third clock, and the second clock having a second predetermined phase offset relative to the third clock.

Abstract: A system that transmits signals through a communication channel. During operation, the system receives a sequence of bits for transmission through the communication channel. While transmitting a given bit, the system determines if the given bit has the same state as the previously transmitted bit. If so, the system uses a voltage-mode driver to drive a signal through the communication channel. Otherwise, the system uses a current source coupled to the voltage-mode driver to boost the drive-level of the voltage-mode driver. Note that the current source supplies a current to the communication channel without changing the impedance of the voltage-mode driver. In this way, the present invention compensates for frequency dependant losses in the communication channel without sacrificing impedance matching and without substantially increasing power consumption.

Abstract: A system for receiving data on a communication channel. The system examines the state of a bit that was previously received on the channel. If the state of the previously received bit was high, the system looks for a falling edge while receiving a subsequent bit on the channel. Otherwise, the system looks for a rising edge while receiving the subsequent bit on the channel. While looking for a rising edge or looking for a falling edge, the system samples a signal on the channel at discrete time steps within a symbol interval, wherein the symbol interval is a time period during which the signal can change states. The specific discrete time step at which the signal changes state is associated with a specific decoded output symbol. Note that the signal can also convey information by not changing states.

Abstract: An apparatus and method for maintaining a state during a power load change. The apparatus of one embodiment includes a voltage controller coupled to receive a signal from a detector of current change. The detector of current change in this embodiment is coupled to detect change in the current level at a microprocessor and signal a voltage controller of such change, which in turn causes a change in the voltage supplied to the microprocessor. An embodiment of the method comprises using a current detector in detecting current change in a microprocessor, determining according to the current change the power level that is needed to be maintained and increasing the voltage level for a predetermined amount of time to compensate for (any) voltage droop. In an alternative embodiment, a change in power is determined before the change occurs and as such determines the power level needed at the microprocessor.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: One embodiment of the present invention provides a system that uses encoded memory control signals to reduce pin count on chips that generate and drive memory control signals. During operation, the system receives encoded memory control signals from a memory controller, wherein the memory control signals were encoded to reduce the number of memory control signals, and wherein the encoded memory control signals are received at a buffer chip, which is external to the memory controller. Next, the system decodes the encoded memory control signals on the buffer chip to restore the memory control signals, and then drives the memory control signals from the buffer chip to corresponding memory modules in the system memory. By transferring the memory control signals in encoded form from the memory controller to the buffer chip, fewer pins are required on both the memory controller chip and the buffer chip.