Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

Abstract: A scalp cooling apparatus, method, and system that may include an inner scalp cap, an intermediate scalp covering, and an outer scalp cap. The inner scalp cap may be fluidly coupled to a cooling device, that would allow a cooling fluid to traverse the fluid chambers within a set of sections of the inner scalp cap. The inner scalp covering can be constructed of a thermally conductive material. The intermediate scalp covering can be constructed of a thermally neutral material. The outer scalp covering can be constructed of a thermally resistant material. The outer scalp covering may have a first securing mechanism, and a second securing mechanism, that allow the outer scalp covering to be dynamically adjusted and secured against a patient's scalp via the first securing mechanism and the second securing mechanism. The inner scalp cap may be created from a scan of a patient's head, that can then be utilized as an interpolated parametric model may be utilized to generate an output file.

Abstract: A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.

Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.

Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

Abstract: A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.

Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.

Abstract: An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.

Abstract: A spinlock circuit connected to one or more first processors through one or more broadside interfaces. The spinlock circuit is configured to receive a plurality of requests for use of a computing resource from one or more first processors, and reply to each of the plurality of requests within a single clock cycle of the one or more first processors. The spinlock circuit can reply to each of the plurality of requests within a single clock cycle of the one or more first processors by alternately assigning the computing resource to a requesting processor from among the one or more first processors or indicating to the requesting processor from among the one or more first processors that the computing resource is not available.

Abstract: A method for the prevention of the onset of pulmonary oxygen toxicity and/or reduction of decrements of pulmonary function due to pulmonary oxygen toxicity comprising administration of a prophylactically effective amount of an anticholinergic, optionally together with a pharmaceutically acceptable excipient.

Abstract: A set of volatile organic compounds is provided, comprising Benzene, 2,3,4-trimethyl-Pentane, 1,4-dimethyl-, trans-Cyclohexane, 2,2,4-trimethyl-Hexane, 1,7,7-trimethyl-Tricyclo[2.2.1.0(2,6)]heptane, and 4-ethyl-3-Octene for breath analysis. Methods of identifying these VOCs and use thereof in diagnosing, monitoring the onset of pulmonary toxicity are also disclosed.

Abstract: A set of volatile organic compounds is provided, comprising Benzene, 2,3,4-trimethyl-Pentane, 1,4-dimethyl-, trans-Cyclohexane, 2,2,4-trimethyl-Hexane, 1,7,7-trimethyl-Tricyclo[2.2.1.0(2,6)]heptane, and 4-ethyl-3-Octene for breath analysis. Methods of identifying these VOCs and use thereof in diagnosing, monitoring the onset of pulmonary toxicity are also disclosed.

Abstract: A system and method of thermal management of electrical and electronic systems and components that adequately maintains the temperatures of the system electronics and electrical devices within reliable limits during various postulated system malfunctions. The system and method use a phase change material (PCM). In at least some embodiments, the PCM is disposed such that, if a flow of coolant ceases when primary and backup control circuits are energized, primary control circuit temperature will exceed a predetermined temperature within a first time period after the flow of coolant ceases, and backup control circuit temperature will exceed the predetermined temperature a second time period, which is greater than the first time period, after the flow of coolant ceases.

Abstract: A system and method of thermal management of electrical and electronic systems and components that adequately maintains the temperatures of the system electronics and electrical devices within reliable limits during various postulated system malfunctions. The system and method use a phase change material (PCM). In at least some embodiments, the PCM is disposed such that, if a flow of coolant ceases when primary and backup control circuits are energized, primary control circuit temperature will exceed a predetermined temperature within a first time period after the flow of coolant ceases, and backup control circuit temperature will exceed the predetermined temperature a second time period, which is greater than the first time period, after the flow of coolant ceases.