Abstract: A digital predetection signal processor having a main channel processor, a dual path processor and at least two digital filters for filtering digital guidance signals before the signals are input into the main channel and dual processing path processors. The digital filters are each programmable to digitally filter the digital guidance signals to thereby minimize output signal error. The processor further includes a circuit for performing base 10 logarithmic calculations of a binary signal in a digital system for optimizing accuracy of the calculation, and a priority encoder for determining a most significant bit position of the binary number, with the most significant bit representing a base 2 logarithmic integer component of the input binary signal.

Abstract: A digital predetection signal processor having a main channel processor, a dual path processor and at least two digital filters for filtering digital guidance signals before the signals are input into the main channel and dual processing path processors. The digital filters are each programmable to digitally filter the digital guidance signals to thereby minimize output signal error. The processor further includes a circuit for performing base 10 logarithmic calculations of a binary signal in a digital system for optimizing accuracy of the calculation, and a priority encoder for determining a most significant bit position of the binary number, with the most significant bit representing a base 2 logarithmic integer component of the input binary signal.