Abstract: A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.

Abstract: A system and method for testing digital to analog converters (DAC) in a serial interface having a comparator to receive an input signal and a local offset signal is disclosed. A first DAC selectably provides one of a global offset to the input signal during a normal mode of operation and a first test signal to the comparator during a test mode of operation. A second DAC selectably provides one of the local offset signals to the comparator during the normal mode of operation and a second test signal to the comparator during the test mode of operation. A test module may cause the first DAC to determine a first test signal to provide to the local offset input of the comparator and may cause the second DAC to incrementally change a test signal provided to the comparator.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.

Abstract: An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A thermal conductive tape article is provided which is adhered to the surface of an integrated circuit device to dissipate heat from the device. The thermal conductive tape article is preferably corrugated and may have a number of configurations providing an expanded surface area. The corrugated tape article may also have a metal strip bonded to one or both sides of the tape article to form a single-faced or double-faced corrugated tape article. The tape article is preferably made of copper or aluminum.