Patents by Inventor William D. Darlington

William D. Darlington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7670760
    Abstract: A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: March 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinmiao James Shen, Jonathan L. Cobb, William D. Darlington, Brian J. Fisher, Mark D. Hall, Vikas R. Sheth, Mehul D. Shroff, James E. Vasek
  • Patent number: 7157377
    Abstract: A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: January 2, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cesar M. Garza, William D. Darlington, Stanley M. Filipiak, James E. Vasek