Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A system and method for maintaining the upset rate of microcircuits within acceptable limits, while optimizing performance and, optionally, not increasing power consumption. The system comprises a variable power supply, which supplies power to the microcircuit; a controller which provides an instructions to the variable power supply to vary voltage depending on susceptibility to upsets; and an actuator for sending an actuating signal to the controller. The system can include a variable frequency clock for varying the clock rate of the microcircuit and the controller can send instructions to vary the clock rate in order to keep power consumption constant.

Abstract: A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured. The inventive processor is implemented on a single substrate as a network of clusters of elements. Each cluster includes a crossbar switching node to which a plurality of elements is connected via ports. Additional ports on the crossbar switching node connect to the switching nodes of nearest neighbor clusters. The crossbar switching nodes allow pathways to be programmably set between any of the ports, and any pathway may be set to be either registered or unregistered. The use of clusters of processing elements allows complete freedom of local connectivity for effective configuration of many different processing functions. Wide area interconnection is more restricted, but, since it is less used, does not significantly restrict configurability.

Abstract: A communication path includes N channels or information pathways, each of which is bidirectional, i.e. each channel may be set to either send or receive. The number of send channels (S) and receive channels (R) is programmably set, such that S+R=N. The total bandwidth is N*B, where B is the bandwidth of each channel, and the send and receive bandwidths can be adjusted to any values such that N*B≧(S*B+R*B), on an as-needed basis depending on the processing algorithms being executed.

Abstract: A system and method for maintaining the upset rate of microcircuits within acceptable limits, while optimizing performance and, optionally, not increasing power consumption. The system comprises a variable power supply, which supplies power to the microcircuit; a controller which provides an instructions to the variable power supply to vary voltage depending on susceptibility to upsets; and an actuator for sending an actuating signal to the controller. The system can include a variable frequency clock for varying the clock rate of the microcircuit and the controller can send instructions to vary the clock rate in order to keep power consumption constant.

Abstract: Techniques for converting input data from a multiplicity of sources that are mutually asynchronous, to a single, common synchronous format for local processing by an information processor. Logical operations are described which control first-in-first-out (“FIFO”) buffers to align all inputs to a predetermined point in the data flow or processing sequence, and which maintain clock-by-clock alignment of the input data sequences for an indefinite period of time thereafter.

Abstract: A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the illustrative embodiment, the first circuit is fabricated with silicon germanium (SiGe) technology and the second circuit is fabricated with complementary metal-oxide semiconductor (CMOS) technology. In an illustrative application, the first circuit includes a high-speed data receiver and a high-speed data transmitter. In the illustrative implementation, the data receiver includes a line receiver, a data and clock recovery circuit, and a demultiplexer and the data transmitter includes a multiplexer, a data and clock encoding circuit, and a line driver.

Abstract: A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured. The inventive processor is implemented on a single substrate as a network of clusters of elements. Each cluster includes a crossbar switching node to which a plurality of elements is connected via ports. Additional ports on the crossbar switching node connect to the switching nodes of nearest neighbor clusters. The crossbar switching nodes allow pathways to be programmably set between any of the ports, and any pathway may be set to be either registered or unregistered. The use of clusters of processing elements allows complete freedom of local connectivity for effective configuration of many different processing functions. Wide area interconnection is more restricted, but, since it is less used, does not significantly restrict configurability.

Abstract: A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the illustrative embodiment, the first circuit is fabricated with silicon germanium (SiGe) technology and the second circuit is fabricated with complementary metal-oxide semiconductor (CMOS) technology. In an illustrative application, the first circuit includes a high-speed data receiver and a high-speed data transmitter. In the illustrative implementation, the data receiver includes a line receiver, a data and clock recovery circuit, and a demultiplexer and the data transmitter includes a multiplexer, a data and clock encoding circuit, and a line driver.

Abstract: A test circuit that includes a scan path having serially coupled scan flip-flops clocked by a system clock signal, an index counter clocked by the system clock for providing an index output for tracking data in the scan path, a control circuit clocked by a test clock signal for receiving scan input data from an external source and for providing output data to the external source, an input memory for receiving scan input data from the control circuit, an output memory for receiving the output of the scan path, and a selection circuit having a first input for receiving the output of the scan path, a second input for receiving scan input data from the input memory, and an output connected to the input of the scan path.

Abstract: A technique to modify the input data to any system so as to cancel errors in the transfer function of that system. The system error response to each possible input amplitude transition is determined. A compensating input sequence is calculated which compensates for this error. The error-correcting sequence is stored in memory for each possible transition. These pattern sequences exactly cancel errors in the response to each of the possible, individual sample-to-sample transitions. For each of any series of input data sample transitions, the appropriate correction sequence is recalled from memory. The composite corrected input is the sum of Y correction sequences from Y preceding sample transitions.

Abstract: A system for preheating electronic components on a printed wiring board or other interconnecting substrate prior to application of voltage to the components in extreme cold temperature environments. Copper traces are employed as embedded heater elements. A control circuit disables operation of an on-board DC/DC switching converter used to provide power to the electronic components until the board has reached a threshold temperature during a preheating period. Thereafter, the heater operation is synchronized with the operation of the switching converter, such that the temperature can be maintained, yet total power supply current to the board never exceeds a predetermined maximum level.

Abstract: A clock distribution system including a variable delay circuit responsive to a reference clock signal having a fixed clock pulse width and a variable clock period for providing a delayed clock signal, an inverter for inverting the delayed clock signal to an inverted delayed clock signal, a clock tree for providing multiple replicas of the inverted delayed clock signal, a comparator responsive to the reference clock signal and a selected one of the multiple replicas of the inverted delayed clock signal for controlling the variable delay circuit such that the selected replica is delayed by one clock pulse width relative to the reference clock signal. Also disclosed is a shift register controlled variable delay line that can be implemented in the variable delay circuit.