Patents by Inventor William D. French

William D. French has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393787
    Abstract: An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 19, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, William D. French, Ann Gabrys
  • Patent number: 10481628
    Abstract: Power consumption is sensed for individual subsystems of an agricultural machine. Visual indicia are generated, that are indicative of the sensed power consumption, for each individual subsystem. A user interface mechanism is controlled to display the visual indicia, indicating power consumption of the individual subsystems on the harvesting machine.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 19, 2019
    Assignee: Deere & Company
    Inventor: William D. French, Jr.
  • Publication number: 20190164934
    Abstract: An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Dok Won Lee, William D. French, Ann Gabrys
  • Patent number: 10281905
    Abstract: In an agricultural machine, sensor signal variability is identified, over a period of time. A control system deadband is identified, based upon the sensor signal variability. A control system uses the control system deadband to control the agricultural machine.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 7, 2019
    Assignee: Deere & Company
    Inventor: William D. French, Jr.
  • Patent number: 10234837
    Abstract: Sensor signal values, indicative of a performance metric, are received and recorded over a given time period. The sensor signal values are aggregated, and a threshold signal value is identified based on the aggregated sensor signal value. A set of control signals, for controlling subsystems on the mobile machine, are generated based on the identified threshold signal value, and the subsystems are controlled based upon the control signals.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 19, 2019
    Assignee: Deere & Company
    Inventor: William D. French, Jr.
  • Patent number: 9961831
    Abstract: A sensor generates a sensor signal indicative of a sensed variable. A first filter is applied to the sensor signal, and filters the sensor signal based on a first set of sensor data, to generate a first filtered signal. A second filter is applied to the sensor signal, based on a second set of sensor data that is greater than the first set of sensor data, to generate a second filtered sensor signal. The first and second filtered sensor signals are compared to generate a control signal that can be used to control a controllable subsystem of a mobile machine.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 8, 2018
    Assignee: Deere & Company
    Inventor: William D. French, Jr.
  • Publication number: 20180116112
    Abstract: A sensor generates a sensor signal indicative of a sensed variable. A first filter is applied to the sensor signal, and filters the sensor signal based on a first set of sensor data, to generate a first filtered signal. A second filter is applied to the sensor signal, based on a second set of sensor data that is greater than the first set of sensor data, to generate a second filtered sensor signal. The first and second filtered sensor signals are compared to generate a control signal that can be used to control a controllable subsystem of a mobile machine.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 3, 2018
    Inventor: William D. French, JR.
  • Patent number: 9807932
    Abstract: A set of sensor inputs are received in an agricultural machine. The sensor inputs are indicative of sensed or measured variables. A probabilistic control system probabilistically infers values for another set of variables and generates a set of control signals based on the probabilistically inferred values.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: November 7, 2017
    Assignee: Deere & Company
    Inventors: William D. French, Jr., Aaron J. Bruns, Janos Kis
  • Publication number: 20170094901
    Abstract: A set of sensor inputs are received in an agricultural machine. The sensor inputs are indicative of sensed or measured variables. A probabilistic control system probabilistically infers values for another set of variables and generates a set of control signals based on the probabilistically inferred values.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: William D. French, JR., Aaron J. Bruns, Janos Kis
  • Publication number: 20170090445
    Abstract: Sensor signal values, indicative of a performance metric, are received and recorded over a given time period. The sensor signal values are aggregated, and a threshold signal value is identified based on the aggregated sensor signal value. A set of control signals, for controlling subsystems on the mobile machine, are generated based on the identified threshold signal value, and the subsystems are controlled based upon the control signals.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 30, 2017
    Inventor: William D. French, JR.
  • Publication number: 20170083035
    Abstract: Power consumption is sensed for individual subsystems of an agricultural machine. Visual indicia are generated, that are indicative of the sensed power consumption, for each individual subsystem. A user interface mechanism is controlled to display the visual indicia, indicating power consumption of the individual subsystems on the harvesting machine.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: William D. French, JR.
  • Publication number: 20170083006
    Abstract: In an agricultural machine, sensor signal variability is identified, over a period of time. A control system deadband is identified, based upon the sensor signal variability. A control system uses the control system deadband to control the agricultural machine.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventor: William D. French, JR.
  • Publication number: 20150340422
    Abstract: A method of manufacturing an inductor on a wafer level process that can operate at 20 MHz with good efficiency and a high inductance density is disclosed, wherein the inductor design allows high frequency operation, low RDSON values and high efficiency.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: Dok Won Lee, William D. French, Andrei Papou
  • Publication number: 20150340338
    Abstract: An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: Dok Won Lee, William D. French, Ann Gabrys
  • Patent number: 8629027
    Abstract: An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or 182) of a semiconductor body. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A more heavily doped pocket portion (250 or 290) of the body material extends largely along only the source. The source has a main source portion (240M or 280M) and a more lightly doped lateral source extension (240E or 280E). The drain has a main portion (242M or 282M) and a more lightly doped lateral drain extension (242E or 282E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: January 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Patent number: 8410549
    Abstract: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E).
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Jeng-Jiun Yang, William D. French, Sandeep R. Bahl, D. Courtney Parker
  • Patent number: 8377768
    Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, William D. French, Donald M. Archer, Jeng-Jiun Yang, Sandeep R. Bahl, D. Courtney Parker
  • Patent number: 8304835
    Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Sandeep R. Bahl, William D. French, Jeng-Jiun Yang, Donald M. Archer, D. Courtney Parker, Prasad Chaparala
  • Patent number: 8304320
    Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: November 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, William D. French, Constantin Bulucea
  • Publication number: 20120264263
    Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.
    Type: Application
    Filed: November 9, 2011
    Publication date: October 18, 2012
    Inventors: Constantin Bulucea, William D. French, Donald M. Archer, Jeng-Jiun Yang, Sandeep R. Bahl, D. Courtney Parker