Abstract: A high power, flip-chip microwave monolithic integrated circuit (MMIC) assembly (30) has a high power microwave monolithic integrated circuit (MMIC) having a surface with an active area (72) in which heat is generated. The assembly also has a host substrate (34). A thermally conductive bump (51) formed over the surface of the MMIC has a first portion (51') in close proximity to and in thermal communication with the active area (72) of the MMIC and a second portion (51") which is in close proximity to and in thermal communication with the host substrate (34). The second portion (51") of the thermal bump (51) has a greater cross-sectional area than the first portion (51'). A multi-layer, multi-exposure method of manufacturing the improved thermal bump (51) includes several steps. A plating membrane (80) is formed on a surface of the MMIC (32). A first layer of negative photoresist is applied to the surface of the plating membrane (80), and is exposed with a first masked pattern of light.

Abstract: A high power, flip-chip microwave monolithic integrated circuit (MMIC) assembly (30) has a high power microwave monolithic integrated circuit (MMIC) having a surface with an active area (72) in which heat is generated. The assembly also has a host substrate (34). A thermally conductive bump (51) formed over the surface of the MMIC has a first portion (51') in close proximity to and in thermal communication with the active area (72) of the MMIC and a second portion (51") which is in close proximity to and in thermal communication with the host substrate (34). The second portion (51") of the thermal bump (51) has a greater cross-sectional area than the first portion (51'). A multi-layer, multi-exposure method of manufacturing the improved thermal bump (51) includes several steps. A plating membrane (80) is formed on a surface of the MMIC (32). A first layer of negative photoresist is applied to the surface of the plating membrane (80), and is exposed with a first masked pattern of light.

Abstract: A process is provided for passivating surfaces (12') of III-V microwave monolithic integrated circuit (MMIC) flip chips (40). Essentially, two cured, patterned polyimide layers (10, 28) are applied, one on the chip surface supporting a gold-plated bridge (26) and passivating the surface and the other over the gold-plated bridge to passivate the bridge surface. Further, a silver-titanium composite layer (32) is deposited over a gold-plated bump-post (24), which is then covered by a silver-plated bump (38), in order to prevent scavenging of gold from the bump-post by a subsequent Pb-Sn reflow solder process used to mount the chip to a metallized ceramic substrate. The process of the invention facilitates a more compatible reflow solder silk-screening process with passivated III-V MMIC flip chips, resulting in a more uniform and consistent solder thickness and relieving a tight tolerance requirement on the plated silver bump height uniformity.

Abstract: A gallium arsenide Monolithic-Microwave-Integrated-Circuit (MMIC) flip chip or other microelectronic circuit structure (10) includes a plated gold bridge (28) which serves as metal interconnect crossover between sites (24,-26) on a substrate (12). A first inorganic dielectric passivation layer (16), preferably of silicon dioxide, is formed under and supports the bridge (28). A second inorganic dielectric passivation layer (30), also preferably of silicon dioxide, is formed over and encapsulates the bridge (28) and the chip surface. A titanium/gold/titanium membrane (22) is formed under the bridge (28) to enable adhesion of the bridge (28) to the first passivation layer (16) and form plating contacts for the bridge (28). A contact bump post (38) is formed in a bump hole or via (32) which extends through the first and second passivation layers (16,30) to a bump contact site (34) on the substrate (12).