Abstract: A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

Abstract: A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

Abstract: A solder bumping method and structure for fine solder bump pitches. The method makes use of a semiconductor device having an input/output pad whose surface is provided with a solderable metal layer that serves as the UBM of the solder bump. A sacrificial layer is formed on the surface of the device to surround the metal layer. A plating seed layer is then formed on the metal layer and the surrounding surface of the sacrificial layer, after which a mask is formed on the seed layer and a via is defined in the mask to expose portions of the seed layer overlying the metal layer and the sacrificial layer. A solder material is deposited on the seed layer exposed within the via. The mask is then removed, followed by removal of a portion of the seed layer that is not covered by the solder material, leaving intact that portion of the seed layer beneath the solder material.

Abstract: A carrier device (10) is provided for transferring solder bumps (16) to a surface of a flip chip integrated circuit device (18). The carrier device (10) is equipped with cavities (12) on its surface for receiving and retaining solder material (14), by which the solder material (14) can be transferred to the flip chip (18) as molten solder bumps (16). The cavities (12) are located on the surface of the carrier device (10) such that the location of the solder material (14) will correspond to the desired solder bump locations on the flip chip (18) when the carrier device (10) is registered with the flip chip (18). The size of the cavities (12) can be controlled in order to deliver a precise quantity of solder material (14) to the flip chip (18).

Abstract: A flip chip integrated circuit device (110) is provided having a surface, a perimeter, and solder bumps (112) located on the surface. At least one solder bump (112), and preferably a plurality of solder bumps (112), are spaced apart from the perimeter of the device (110). Electrically conductive runners (118) extend from the perimeter of the device (110) to each of those solder bumps (112) that are spaced apart from the perimeter, so as to electrically interconnect the solder bumps (112) to a point, such as a pad (116), at the perimeter. As a result, not all of the solder bumps (112) employed by the device (110) need be accommodated at the perimeter of the device (110), such that the size and number of the solder bumps (112) does not dictate the size of the device (110).

Abstract: A microwave radar transceiver assembly (30) includes a monolithic microwave integrated circuit (MMIC) chip (58) having a coplanar waveguide transmssion lines (100, 102, 104) formed on the same surface (58a) as the electronic elements thereof. Coplanar waveguide transmission lines (68, 70, 72) are also formed on a surface (62a) of a substrate (62). The transceiver chip (58), in addition to other chips (56, 60), are mounted on the substrate (62) in a flip-chip arrangement, with the respective surfaces (58a, 62a) on which the transmission lines (100, 102, 104; 68, 70, 72) are formed facing each other.

Abstract: A coplanar waveguide based microwave monolithic integrated circuit (MMIC) oscillator chip (14) having an active oscillator element (16) and a resonant capacitor (18) formed thereon is flip-chip mounted on a dielectric substrate (12). A resonant inductor (22) is formed on the substrate (12) and interconnected with the resonant capacitor (18) to form a high Q-factor resonant circuit for the oscillator (10). The resonant inductor (22) includes a shorted coplanar waveguide section (24) consisting of first and second ground strips (24b,24c), and a conductor strip (24a) extending between the first and second ground strips (24b,24c) in parallel relation thereto and being separated therefrom by first and second spaces (26a,26b) respectively. A shorting strip (24d) electrically interconnects adjacent ends of the conductor strip (24a) and first and second ground strips (24b,24c) respectively.

Abstract: A diaphragm is formed in a silicon chip by etching a rectangular cavity in one side thereof and piezoresistive resistors are formed in the other surface of the chip to sense stress changes on the diaphragm due to pressure changes. At least one resistor is placed along the edge of the diaphragm where a sharp stress peak occurs. To avoid the problem of inaccurate placement of the resistor relative to the peak, the resistor is slanted with respect to the stress ridge at a small angle of 10.degree. to 20.degree.. This makes the resistor placement and cavity alignment much less critical thereby assuring greater uniformity of response from one sensor to another at the expense of signal size for a given pressure change on the device.