Abstract: An electronic system located upon a single semiconductor substrate including a plurality of isolated electronic subsystems located upon the semiconductor substrate. Each electronic subsystem includes a plurality of input/output lines. Several information bus lines are included that are connected to addressable transistors located between the individual bus lines and the input/output lines. An addressing means is connected to the addressable transistors for addressing each of the addressable transistors and for providing a first state signal indicating an ON condition to the first select group of said addressable transistors, electrically connecting the information bus lines to the input/output lines and a second state signal indicating an OFF condition to a second selected group of the addressable transistors, electrically isolating the information bus lines from the input/output lines. The addressable transistors maintain the state signal indicated condition.