Patents by Inventor William D. Llewellyn

William D. Llewellyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10015608
    Abstract: In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 3, 2018
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Philip Crawley, William D. Llewellyn, Majid Shushtarian, Earl D. Schreyer
  • Publication number: 20170303057
    Abstract: In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 19, 2017
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Philip CRAWLEY, William D. LLEWELLYN, Majid SHUSHTARIAN, Earl D. SCHREYER
  • Patent number: 9729986
    Abstract: In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: August 8, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Philip Crawley, William D. Llewellyn, Majid Shushtarian
  • Patent number: 9647546
    Abstract: Devices and methods provide a voltage regulating device including voltage supply circuitry configured to receive a first voltage, generate at least a second voltage based on the first voltage, and output an output voltage, the output voltage being one of the first voltage and the second voltage based on a voltage selection signal; regulator circuitry configured to switch between the output voltage and a reference potential based on a control signal; and control circuitry configured to generate the control signal, the control signal having a first duty cycle if the output voltage is the first voltage and a second duty cycle if the output voltage is the second voltage, the control circuitry configured to adjust the second duty cycle based on, at least in part, a droop voltage in the regulator circuitry.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: May 9, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Patent number: 9083322
    Abstract: An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: July 14, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Publication number: 20150162834
    Abstract: Devices and methods provide a voltage regulating device including voltage supply circuitry configured to receive a first voltage, generate at least a second voltage based on the first voltage, and output an output voltage, the output voltage being one of the first voltage and the second voltage based on a voltage selection signal; regulator circuitry configured to switch between the output voltage and a reference potential based on a control signal; and control circuitry configured to generate the control signal, the control signal having a first duty cycle if the output voltage is the first voltage and a second duty cycle if the output voltage is the second voltage, the control circuitry configured to adjust the second duty cycle based on, at least in part, a droop voltage in the regulator circuitry.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 11, 2015
    Inventor: William D. Llewellyn
  • Patent number: 8866544
    Abstract: This document discusses, among other things, a modulator including a first integrator configured to receive an input signal and a first feedback signal from an output stage, a second integrator configured to receive an output of the first integrator and a second feedback signal, and a comparator configured to be coupled to a regulated supply voltage, to receive an output of the second integrator and a modulation signal, and to provide a pulse width modulated representation of the input signal. The output stage is configured to be coupled to an unregulated supply voltage, and the second feedback signal can include a representation of an output of the comparator configured to reduce artifacts in the pulse width modulated representation of the input signal induced by changes in an amplitude of the unregulated supply voltage.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Patent number: 8831230
    Abstract: This document discusses apparatus and methods for configuring and providing crosstalk cancellation to maintain channel separation in a multi channel system. In an example, an amplifier circuit can include a crosstalk cancellation circuit configured to reduce crosstalk from a first output to a second load and from a second output to a first load where the first load and the second load share a return path.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: William D. Llewellyn, Carmine Cozzolino
  • Publication number: 20140126730
    Abstract: In one general aspect, a method can include calculating, at a calibration temperature of a speaker, a calibration parameter through a coil of the speaker in response to a first test signal, and can include sending a second test signal through the coil of the speaker. The method can also include measuring a parameter through the coil of the speaker based on the second test signal, and calculating a temperature change of the coil of the speaker based on the parameter and based on the calibration parameter at the calibration temperature.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 8, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Philip CRAWLEY, William D. LLEWELLYN, Majid SHUSHTARIAN, Earl D. SCHREYER
  • Patent number: 8638148
    Abstract: This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: January 28, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Publication number: 20130016844
    Abstract: An apparatus includes a capacitor, a current generating circuit communicatively coupled to the capacitor, and a current pulse timing circuit communicatively coupled to the current source circuit. The current timing pulse circuit is configured to time durations of a first plurality of current pulses from the current generating circuit for charging the capacitor and a second plurality of current pulses for discharging the capacitor, and step the durations of the current pulses between a minimum duty cycle and a maximum duty cycle. A cycle of providing the first plurality of current pulses and providing the second plurality of current pulses results in generation of a subsonic pseudo-sinusoidal pulse signal at the capacitor.
    Type: Application
    Filed: July 12, 2011
    Publication date: January 17, 2013
    Inventor: William D. Llewellyn
  • Publication number: 20120262211
    Abstract: This document discusses, among other things, a modulator including a first integrator configured to receive an input signal and a first feedback signal from an output stage, a second integrator configured to receive an output of the first integrator and a second feedback signal, and a comparator configured to be coupled to a regulated supply voltage, to receive an output of the second integrator and a modulation signal, and to provide a pulse width modulated representation of the input signal. The output stage is configured to be coupled to an unregulated supply voltage, and the second feedback signal can include a representation of an output of the comparator configured to reduce artifacts in the pulse width modulated representation of the input signal induced by changes in an amplitude of the unregulated supply voltage.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 18, 2012
    Applicant: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Publication number: 20120262230
    Abstract: This document discusses apparatus and methods for configuring and providing crosstalk cancellation to maintain channel separation in a multi channel system. In an example, an amplifier circuit can include a crosstalk cancellation circuit configured to reduce crosstalk from a first output to a second load and from a second output to a first load where the first load and the second load share a return path.
    Type: Application
    Filed: October 12, 2011
    Publication date: October 18, 2012
    Inventors: William D. Llewellyn, Carmine Cozzolino
  • Publication number: 20120206191
    Abstract: This document discusses, among other things, apparatus and methods for pre-biasing an edge rate controlled output stage of a switch circuit. In an example, a switch circuit can include an output transistor and a pre-bias circuit coupled to the output transistor. The pre-bias circuit can include a pre-bias transistor configured to selectively couple a control node of the output device to a first voltage, and wherein the pre-bias transistor can include a lower threshold voltage than the output transistor.
    Type: Application
    Filed: July 6, 2011
    Publication date: August 16, 2012
    Inventor: William D. Llewellyn
  • Publication number: 20110084746
    Abstract: This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 14, 2011
    Inventor: William D. Llewellyn
  • Patent number: 7821338
    Abstract: A drive current direction between first and second amplifiers can be selected using a received indication of an output current in an at least partially reactive load, and an amplified output signal can be produced using the selected drive current direction and the first and second amplifiers. Further, the first and second amplifiers can be configured to alternate between a pull-up mode and a pull-down mode, each amplifying half of a full wave output signal.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 26, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Publication number: 20100001799
    Abstract: A drive current direction between first and second amplifiers can be selected using a received indication of an output current in an at least partially reactive load, and an amplified output signal can be produced using the selected drive current direction and the first and second amplifiers. Further, the first and second amplifiers can be configured to alternate between a pull-up mode and a pull-down mode, each amplifying half of a full wave output signal.
    Type: Application
    Filed: April 17, 2009
    Publication date: January 7, 2010
    Applicant: Fairchild Semiconductor Corporation
    Inventor: William D. Llewellyn
  • Patent number: 7026866
    Abstract: Techniques for DC offset cancellation are described. According to one embodiment, an amplifier has at least one output and first and second supply rails. The amplifier includes offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail. The offset cancellation logic is further operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: April 11, 2006
    Assignee: Tripath Technology, Inc.
    Inventor: William D. Llewellyn
  • Publication number: 20040227567
    Abstract: Techniques for DC offset cancellation are described. According to one embodiment, an amplifier has at least one output and first and second supply rails. The amplifier includes offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail. The offset cancellation logic is further operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals.
    Type: Application
    Filed: March 23, 2004
    Publication date: November 18, 2004
    Applicant: Tripath Technology, Inc.
    Inventor: William D. Llewellyn
  • Patent number: 6785392
    Abstract: Apparatus and methods for enabling and disabling an amplifier is described. Amplifiers can be enabled and disabled for the sake of power and energy savings and reduction of dissipated heat. The circuit is based on a gain stage and threshold circuitry. A signal associated with an amplifier is introduced into the gain stage. The gain stage amplifies the signal level and provides the amplified signal level to threshold circuitry. The threshold circuitry references the amplified signal level and determines signal states. The control circuitry interprets these signal states to determine when to enable or disable an amplifier. The output of the threshold circuitry can be used to adjust the amplified signal level to oppose drift in the gain stage.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: August 31, 2004
    Assignee: Tripath Technology, Inc.
    Inventor: William D. Llewellyn