Abstract: A dual processor computer system with error checking that stops immediately when a discrepancy is detected between the two processors. The system includes a first processor for executing a series of instructions including input/output instructions. A second processor executes the same instructions independently of and in synchronization with the first processor. Both processors have a processor independent bus interface. All significant processor address, data, and control signals are connected to all peripheral devices by a processor independent I/O bus. A comparison circuit detects discrepancies in the operation of the two lock step processors and provides a signal that immediately stops operation of the processors when an error is detected. Each processor is connected through its associated processor independent bus interface to the comparison circuit and the first processor is also connected through its interface to the I/O bus.

Abstract: A power supply arrangement is disclosed wherein the power supplies (12, 14) share the power requirements of a common load (20) approximately equally and wherein either of the power supplies (12, 14) can act as the "master" while the other power supply acts as the "slave". The arrangement utilizes an integrating differential error amplifier (54), an inverting amplifier (56), and a non-inverting amplifier (58) which are electrically connected between the common load (20) and the power supplies (12, 14) to detect any difference in the output current of the power supplies (12, 14) due to a difference in output voltage, and correct same by increasing the output voltage of the power supply having the lower output voltage until the difference is eliminated. In this manner, either power supply (12, 14) can act as the "master" while the other power supply acts as the "slave".