Abstract: A communications network has a plurality of users connected by virtual circuits to a plurality of service providers. A server has the plurality of users connected thereto. A node provides the plurality of service providers. Both the server and the node are connected to the network. A first session is established between one user and the server, and a second session is established between the node and a selected one of the service providers. A virtual circuit is established linking the first service session and the second service session to establish message transmission between the one user and the selected service provider. A message sent between the user and the service provider is sent over the network, and the message identifies the virtual circuit. Messages between a server and a node are multiplexed by having slots, and a slot contains a message from a sending session to a receiving session.

Abstract: In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits.

Abstract: Devices for interconnection into a digital computer system contain arbitration mechanisms for assigning control of a common communications path among the devices. Several modes of device arbitration are provided for, and the modes may be mixed among devices, and changed during operation of the system, in the system without interfering with communications. The arbitration mechanism requires only a single additional line in the communications pathway, and thus a single additional pin on the integrated circuit on which it is implemented, for the arbitration function. It thus facilitates implementation of the arbitration mechanism along with all other interconnect logic on a single integrated circuit.

Abstract: Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other, the source and destination buffer names are contained right in the transmitted packet.The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed.

Abstract: An arbitration technique for controlling access to a bit-serial bus by multiple nodes in a data processing network. Upon detection of no carrier on the bus (56), a node desiring access to the bus waits a predetermined number of quiet slots (60, 64), each slot being a predetermined interval. If that period elapses without another node's carrier being detected (64), the node desiring access is permitted to transmit (64, 68). For each node, two such delay-interval possibilities are provided, one high slot count (and, hence, low priority) and one low slot count (and, hence, high priority). The delay-interval selection for a node is switched from time to time on a round-robin basis so that all nodes get equal average priority. The high value of the delay interval is N+M+1 slots, where N is the node number and M is the maximum number of nodes allowed on the bus; the low value is N+1 slots. Initially, each node uses the former value.

Abstract: A central processor for use in a data processing system that is adapted for processing sequences of characters. Information identifying a string of characters to be examined, including the memory location for the first character in the sequence and the total number of characters in the sequence, is placed in working registers of the central processor. Other working registers in the central processor receive information corresponding to a predetermined characteristic, which may be a specific character or information identifying another character string. One of several character string instructions then can be processed. In response to a typical character string instructuion, the central processor retrieves each character from the memory and compares it with the predetermined characteristic. Processing continues until either the predetermined characteristic is detected or all the characters in the character string are examined.

Abstract: A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time.

Abstract: A digital data processing system with a central processor for responding to diverse instructions including instructions for calling subroutines. When the central processor executes a calling instruction, the central processor saves information corresponding to the operating environment for the calling routine and then utilizes corresponding information in the subroutine to establish the operating environment for the subroutine. A common return instruction at the completion of each subroutine causes the central processor to retrieve the saved operating information thereby to reestablish the operating environment for the calling routine.

Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.