Patents by Inventor William D. Warner

William D. Warner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9444588
    Abstract: A method for evaluating operation of a receiver comprising an analog front end, a plurality of samplers connected in parallel to the analog front end, the plurality of samplers comprising a plurality of utility samplers, a plurality of data samplers and a plurality of timing samplers, an unrolled decision feedback equalizer (UDFE) connected to outputs of the plurality of data samplers, and a serial input parallel out (SIPO) block connected to an output of the UDFE and outputs of the plurality of utility and timing samplers. The method comprises adjusting settings of the plurality of utility samplers to sweep across a range of interest, at each of a plurality of points comparing a selected output of one of the plurality of utility samplers at that point to an output of one of the plurality of data samplers to detect an error event, and, accumulating the error events.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: September 13, 2016
    Inventors: Ognjen Katic, William D. Warner
  • Patent number: 9426004
    Abstract: A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: August 23, 2016
    Assignee: Microsemi Storage Solutions (U.S.), Inc.
    Inventor: William D. Warner
  • Patent number: 9344272
    Abstract: Apparatus and methods reduce channel-dependent phase detector offset and/or gain errors. A conventional Mueller-Muller phase detector places a main cursor at the midpoint of a pre-cursor and a post-cursor. However, for example, when the impulse response of an associated transmission line is not symmetric, the main cursor can be misaligned by conventional Mueller-Muller techniques. By providing a replica clock and data recovery path, trial and error experiments on the phase detector offset and/or gain can be performed, and relatively good values found for the phase detector offset and/or gain without disturbing the reception of data by the phase detector that is being used to receive data. These settings can then be used by the phase detector that is being used to receive data, which can improve the bit error rate of the phase detector.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 17, 2016
    Assignee: Microsemi Storage Solutions, Inc.
    Inventors: Anthony Eugene Zortea, William D. Warner
  • Patent number: 9143371
    Abstract: A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 22, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventor: William D. Warner
  • Patent number: 9071320
    Abstract: Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A Mueller-Muller circuit obtains timing information for a received signal in which the receiving device samples the signal once per baud period.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 30, 2015
    Assignee: PMC-Sierra, Inc.
    Inventors: William D. Warner, Anthony Eugene Zortea
  • Patent number: 9020022
    Abstract: A SerDes receiver comprising: an input for receiving a signal, the signal having a baud rate; an Analog Finite Impulse Response equalizer (AFIR) for equalizing the received signal, the AFIR comprising: a pre-cursor tap having a pre-cursor coefficient; a cursor tap having a cursor coefficient, the cursor coefficient being constrained to a non-negative value; and a post-cursor tap having a post-cursor coefficient; an adaptation block coupled to the AFIR, the adaptation block configured to adjust the pre-cursor coefficient and the post-cursor coefficient based on the received signal, the adaptation block further being configured to constrain the values of the pre-cursor and post-cursor coefficients to be non-positive.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 28, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventor: William D. Warner
  • Patent number: 8995518
    Abstract: Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 31, 2015
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Paul V. Yee, William D. Warner
  • Patent number: 8989250
    Abstract: Methods and circuits for equalizing a linear response in an observation path of a digital pre-distorter. A method comprises generating observed signals in an observation path based on observing a transmit signal; down-converting the observed signals into intermediate frequencies using different LO frequencies; calculating a ratio using the intermediate frequencies; and equalizing the linear response of the observation path on the observed signals using the ratio. An apparatus comprises a directional coupler for observing a transmit signal and generating observed signals; a down-converter for converting the observed signals into intermediate frequencies using different LO frequencies; and an adaptive estimator for calculating a ratio using the intermediate frequencies and using the ratio to equalize a linear response from the observation path on the observed signals.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: William D. Warner, Andrew S. Wright, Bartholomeus T. W. Klijsen, Derek J. W. Ho
  • Patent number: 8948325
    Abstract: A method and apparatus to digitally remove in-band non-linear signal distortion caused by a radio frequency (RF)/intermediate frequency (IF) receiver circuit that has non-linearities, which are further affected by low-IF ADC sample aliasing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventors: William D. Warner, Clarence K. L. Tam
  • Patent number: 8942334
    Abstract: Apparatus and methods reduce channel-dependent phase detector offset and/or gain errors. A conventional Mueller-Muller phase detector places a main cursor at the midpoint of a pre-cursor and a post-cursor. However, for example, when the impulse response of an associated transmission line is not symmetric, the main cursor can be misaligned by conventional Mueller-Muller techniques. By providing a replica clock and data recovery path, trial and error experiments on the phase detector offset and/or gain can be performed, and relatively good values found for the phase detector offset and/or gain without disturbing the reception of data by the phase detector that is being used to receive data. These settings can then be used by the phase detector that is being used to receive data, which can improve the bit error rate of the phase detector.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: January 27, 2015
    Assignee: PMC-Sierra, Inc.
    Inventors: Anthony Eugene Zortea, William D. Warner
  • Patent number: 8923460
    Abstract: Methods and systems are provided for processing electrical signals derived from coherent dual polarization optical signals. A method comprises receiving first and second input signals, filtering the input signals by first and second complex SISO FIR to generate filtered input signals, filtering the filtered input signals and the input signals by first and second two-by-two matrix filters each having four branches to respectively generate equalized filtered signals and equalized signals, and, adapting the first and second complex SISO FIR filters based on the equalized signals and the equalized filtered signals.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 30, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventors: Xiaofeng Wang, William D. Warner
  • Patent number: 8816886
    Abstract: A method and apparatus for controlling the effective gain of an ADC when the ADC is occasionally or continuously calibrated using the statistics of the input signal and when the statistics are not stationary.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 26, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventors: William D. Warner, Anthony Eugene Zortea, Jim Guziak
  • Patent number: 8693596
    Abstract: Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A main signal path includes a Mueller-Muller based timing error detector (MM TED). The main signal path generates a main error signal for clock recovery. A secondary signal path that includes a secondary MM TED. Each signal path samples soft symbols from a received signal. The sampling of the secondary MM TED is deliberately offset in time. A scale factor applied to the main error signal and to a secondary error signal is adaptively adjusted based on a comparison between the main error signal and the secondary error signal.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: April 8, 2014
    Assignee: PMC-Sierra, Inc.
    Inventors: William D. Warner, Anthony Eugene Zortea
  • Patent number: 8644369
    Abstract: Apparatus and methods generate equalizer coefficients for an equalizer of a receiver. In a high-speed receiver, received symbols can be subject to inter-symbol-interference (ISI). An equalizer can compensate for ISI and improve a bit error rate (BER). However, traditional adaptive techniques to generate coefficients for equalization can generate corrupted coefficients when equalized samples used for adaptation are based on clipped or heavily compressed signals. In certain situations, the clipping rate can be relatively high, such as over 20%. Equalizer performance is improved when the equalized symbols used directly or indirectly for adaptation are selected such that equalized symbols based on clipped input samples are not used for adaptation.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: February 4, 2014
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Paul V. Yee, William D. Warner
  • Patent number: 8611473
    Abstract: For power efficiency, it can be desirable to use a 1-bit ADC or slicer to receive a wired data transmission. A plurality of N samples per baud period are taken. N can be, for example, 4 or more. At least a portion of the samples are included in a window of samples, the size of which is based at least partly on earlier determined values of prior symbols. For example, a polynomial function or other numerical function can be embedded in a lookup table to map previously determined data bits to an address, and the address can be used to control an input of multiplexers to vary the size of the window. The value for a current symbol is determined based at least partly on one or more values within the window of samples.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: December 17, 2013
    Assignee: PMC-Sierra, Inc.
    Inventor: William D. Warner
  • Patent number: 8428113
    Abstract: Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: April 23, 2013
    Assignee: PMC-Sierra, Inc.
    Inventors: Ognjen Katic, Paul V. Yee, William D. Warner
  • Patent number: 8116409
    Abstract: Apparatus and methods detect the presence of an isolated pulse in a communications signal, such as a data signal carrying data for a serializer/deserializer (SerDes). An example of an isolated pulse is a “1” pulse preceded and followed by “0” pulses, or a “0” pulse preceded and followed by a “1” pulse. These isolated pulses can exhibit a narrow pulse width, and under severe jitter conditions, may not align with a baud sample point, which can cause the isolated pulse to be missed, resulting in a data decoding error. By detecting the presence of these isolated pulses and determining the most likely baud period to which they belong, jitter tolerance can be improved for many channel conditions. This can improve jitter tolerance of a SerDes receiver for links that suffer from various sources of Deterministic Jitter (DJ) such as Duty Cycle Distortion (DCD) and Inter-Symbol Interference (ISI).
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: February 14, 2012
    Assignee: PMC-Sierra, Inc.
    Inventor: William D. Warner
  • Patent number: 8023588
    Abstract: Apparatus and methods control predistortion of an RF transmitter. A base station or a mobile station can utilize predistortion to improve linearity characteristics of the RF power amplifier. When used effectively, predistortion limits spectral growth such that the amplified signal complies with regulatory requirements. With respect to bursty signals, specific improvement techniques are disclosed. A first technique is related to adaptation using only a smaller subset of samples of a burst. A second technique is related to selective application of digital predistortion, such as, only under high power conditions for a power amplifier. A third technique is directed to adaptation of less than all of the coefficients. These improvements permit the use of a smaller and less expensive amplifier for a given power class and can lengthen battery life for a mobile unit.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 20, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Jeremy Benson, William D. Warner, Paul V. Yee
  • Patent number: 7656945
    Abstract: A low-complexity digital linear equalizer whose operation and adaptation makes stabilized digital timing recovery practical. The technique is fundamental for the operation of communications receivers employing digital timing recovery, e.g., in a modem. A technique for automatically adjusting the parameters of a digital linear equalizer to compensate for low-pass impairments while maintaining a relatively constant timing characteristic is described.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: February 2, 2010
    Assignee: PMC-Sierra, Inc.
    Inventors: William D. Warner, Paul V. Yee
  • Patent number: 5444697
    Abstract: A method and apparatus are disclosed for achieving symbol (frame) synchronization of digital data in an OFDM channel such as an OFDM/FM radio link. The method and apparatus are suitable for use in a pure ALOHA environment because synchronization is achieved on a frame-by-frame basis. The required bandwidth overhead is less than 10%. The bit-error-rate performance achievable with this technique is within 1.5 dB of the performance assuming ideal synchronization. The method and apparatus provide a three-stage synchronization process. First the onset of an ODFM frame is detected. Second, coarse synchronization is achieved by sampling the received signal, and measuring the correlation between the received signal and a reference signal. Coarse synchronization provides synchronization to within .+-.1/2 sample period. The correlation is preferably carried out in the frequency domain after carrying out a Fast Fourier Transform on the sampled signal data.
    Type: Grant
    Filed: August 11, 1993
    Date of Patent: August 22, 1995
    Assignee: The University of British Columbia
    Inventors: Cybil S. Leung, William D. Warner