Abstract: A method for minimizing fabrication defects in ballast contact to a conductor in monolithically integrated semiconductor devices includes forming a sloping sidewall (318, 424) in both an insulating layer (106, 718) overlying a conductive layer (104, 714) by etching with a an RF biased fluorine based chemistry and an RF biased chlorine based chemistry, respectively, as defined by a single resist layer (108) having a sloped sidewall (212). A ballast layer (526, 726) is deposited on the structure (100, 700) and metal contacts (632, 634, 636, 638, 722) are disposed on the ballast layer (526, 722).

Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.

Abstract: A lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template is provided. The lithographic template (10) and the method of making comprises forming a transparent conductive layer (16) over a substrate (12). A SiCN layer (18) is formed over the transparent conductive layer (16), and a patterning layer (20) formed on the SiCN layer (18). The SiCN layer (18) is converted to an SiO2 layer by applying an O2 plasma (23). The SiO2 layer prevents damage to the transparent conductive layer (16) during cleaning and provides a binding mechanism for the imprint release coating.

Abstract: This invention relates to semiconductor devices, microelectronic devices, micro electro mechanical devices, microfluidic devices, photonic devices, and more particularly to a lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template. The lithographic template (10) is formed having a substrate (12), a transparent conductive layer (16) formed on a surface (14) of the substrate (12) by low pressure sputtering to a thickness that allows for preferably 90% transmission of ultraviolet light therethrough, and a patterning layer (20) formed on a surface (18) of the transparent conductive layer (16).

Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.

Abstract: A direct imprinting process for Step and Flash Imprint Lithography includes providing (40) a substrate (12); forming (44) an etch barrier layer (14) on the substrate; patterning (46) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the substrate; and performing (48) an etch to substantially remove the residual layer. Optionally, a patterning layer (52) may be formed on the substrate (12) prior to forming the etch barrier layer (14). Additionally, an adhesive layer (13) may be applied (42) between the substrate (12) and the etch barrier layer (14).

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Abstract: A selective etch process for step and flash imprint lithography includes providing (30) a substrate (10); forming (32) a transfer layer (12) on the substrate; forming (34) an etch barrier layer (14) on the transfer layer; patterning (36) the etch barrier layer with a template (16) while curing with ultraviolet light through the template, resulting in a patterned etch barrier layer and a residual layer (20) on the transfer layer; performing (38) an etch to substantially remove the residual layer; and performing (40) an etch with a mixture of nitrogen and hydrogen, and more preferably NH3, to substantially remove the portion of the transfer layer not underlying the etch barrier layer.

Abstract: A probe card (40, 55) having probe card probes (36, 56) and a method for fabricating the probe card probes (36, 56). A layer of resist (23) is formed on a plating base (21). The layer of resist (23) is exposed to radiation (32) and developed to provide angled, tapered openings (33) exposing portions of the plating base (22). An electrically conductive material is electroplated on the exposed portions of the plating base (22) and fills the angled, tapered openings (33). The layer of resist (23) and portions of the plating base (22) between the electroplated conductive material are removed. The electrically conductive material forms the probe card probes (36) which are angled and tapered. In addition, the compliant probe card probes (56) may be stair-step shaped.

Abstract: A semiconductor structure (8) comprising a semiconductor chip support structure (9), a circuit board substrate (40) with circuit board substrate probes (36) extending therefrom and a method for fabricating the semiconductor structure (8). The semiconductor chip support structure (9) includes, for example, clips (43, 53) to replaceably mount semiconductor chips (47, 48) to the semiconductor chip support structure (9). The circuit board substrate (40) is mated with the semiconductor chip support structure (9) so that the circuit board substrate probes (36) contact bonding pads (49) on the semiconductor chips (47, 48). If a semiconductor chip (47, 48) becomes damaged, the circuit board substrate (40) may be separated from the semiconductor chip support structure (9) and the damaged semiconductor chip (47, 48) replaced with a good semiconductor chip (47, 48).