Patents by Inventor William David Higdon

William David Higdon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6281106
    Abstract: A method for solder bumping a surface-mount circuit component, as well as electrically and mechanically connecting the component to a conductor on a substrate, and the components and assemblies formed thereby. The method generally entails forming a multilayer metal bump containing discrete layers, including at least one layer of a solder alloy, a first metallic layer having a sufficiently high melting point so as not to melt or deform at the reflow temperature of the solder alloy, and a second metallic layer containing at least one metal that is soluble in the solder alloy. During reflow, the first metallic layer does not collapse, while the solder layer and the second metallic layer readily flow and subsequently bond the first metallic layer to suitable structures on the component and substrate.
    Type: Grant
    Filed: November 25, 1999
    Date of Patent: August 28, 2001
    Assignee: Delphi Technologies, Inc.
    Inventors: William David Higdon, Frank Stepniak, Shing Yeh
  • Patent number: 6251501
    Abstract: A solder bumping method and structure for producing fine-pitch solder bump and which eliminate conventional process compatibility requirements for under bump metallurgy (UBM) and solder bump formation. The method generally entails forming an input/output pad on the surface of a semiconductor device, and then forming a metal layer on the input/output pad that will serve as the UBM of the solder bump. A plating seed layer is then formed on the UBM and on the surrounding surface of the device, after which a mask is formed on the plating seed layer and a via is formed in the mask to expose a portion of the plating seed layer overlying the UBM, and preferably portions of the plating seed layer not overlying the UBM. A solder material is then deposited on the portion of the plating seed layer exposed within the via.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: June 26, 2001
    Assignee: Delphi Technologies, Inc.
    Inventors: William David Higdon, Shing Yeh