Patents by Inventor William David SCHWADERER

William David SCHWADERER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947685
    Abstract: A computer-implemented method can include: a computer program file open request providing read access to text or binary plaintext file data residing on a data storage means; processing the plaintext file data in an input data buffer area following a computer program file data read operation to improve performance by creating a multiplicity of processing threads to perform concurrent, usually non-overlapping encryption processing operations; and an encryption program constructing a previously constructed complex of Pseudo Random Number Generator (PRNG) means to provide on-demand Pseudo Random Number (PRN) values.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: April 2, 2024
    Inventor: William David Schwaderer
  • Patent number: 11947826
    Abstract: A storage system is described. The storage system may include a plurality of storage tiers, each including at least one storage device, each storage device including storage and a controller. Metadata storage may store metadata for an image stored in the plurality of storage tiers, which includes a location in the plurality of storage tiers where the image is stored. A receiver may receive a request to access the image from a host. Retrieval software, executed by a processor, may retrieve the image from the plurality of storage tiers using the location where the image is stored. A transmitter may transmit the image to the host.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sompong Paul Olarig, William David Schwaderer, Chandranil Chakraborttii
  • Patent number: 11893122
    Abstract: A system can include: a plurality of processing Cores; a Package Interconnect communicatively coupled with the plurality of processing Cores; a Configurable LFSR PRV Generator Hardware Array means communicatively coupled with the Package Interconnect; a Galois Multiplication Hardware Accelerator means communicatively coupled with the Package Interconnect; an Extended Euclidian Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect; and a Fischer-Yates Shuffle Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: February 6, 2024
    Inventor: William David Schwaderer
  • Publication number: 20230359749
    Abstract: A computer-implemented method can include: a computer program file open request providing read access to text or binary plaintext file data residing on a data storage means; processing the plaintext file data in an input data buffer area following a computer program file data read operation to improve performance by creating a multiplicity of processing threads to perform concurrent, usually non-overlapping encryption processing operations; and an encryption program constructing a previously constructed complex of Pseudo Random Number Generator (PRNG) means to provide on-demand Pseudo Random Number (PRN) values.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 9, 2023
    Inventor: William David Schwaderer
  • Publication number: 20230239144
    Abstract: A computer-implemented method can include: constructing and initializing Pseudo Random Generator Resources using a multiplicity of secret seed values or secret data values known to a first and second communication device; deriving a session key based, at least in part, on the secret seed, secret data values, Multi-Factor Authentication methods, or Pseudo Random Number Generator Resource generated output; receiving from the first communications device, at the second communications device, data encrypted with the session key or Deterministic Chaos obfuscation methods; and decrypting the data at the second communications device using the session key or Deterministic Chaos de-obfuscation methods.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 27, 2023
    Inventor: William David Schwaderer
  • Publication number: 20230222229
    Abstract: A system can include: a plurality of processing Cores; a Package Interconnect communicatively coupled with the plurality of processing Cores; a Configurable LFSR PRV Generator Hardware Array means communicatively coupled with the Package Interconnect; a Galois Multiplication Hardware Accelerator means communicatively coupled with the Package Interconnect; an Extended Euclidian Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect; and a Fischer-Yates Shuffle Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect.
    Type: Application
    Filed: June 2, 2021
    Publication date: July 13, 2023
    Inventor: William David Schwaderer
  • Publication number: 20220391123
    Abstract: A storage system is described. The storage system may include a plurality of storage tiers, each including at least one storage device, each storage device including storage and a controller. Metadata storage may store metadata for an image stored in the plurality of storage tiers, which includes a location in the plurality of storage tiers where the image is stored. A receiver may receive a request to access the image from a host. Retrieval software, executed by a processor, may retrieve the image from the plurality of storage tiers using the location where the image is stored. A transmitter may transmit the image to the host.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Inventors: Sompong Paul OLARIG, William David SCHWADERER, Chandranil CHAKRABORTTII
  • Patent number: 11449256
    Abstract: A storage system is described. The storage system may include a plurality of storage tiers, each including at least one storage device, each storage device including storage and a controller. Metadata storage may store metadata for an image stored in the plurality of storage tiers, which includes a location in the plurality of storage tiers where the image is stored. A receiver may receive a request to access the image from a host. Retrieval software, executed by a processor, may retrieve the image from the plurality of storage tiers using the location where the image is stored. A transmitter may transmit the image to the host.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 20, 2022
    Inventors: Sompong Paul Olarig, William David Schwaderer, Chandranil Chakraborttii
  • Publication number: 20200110553
    Abstract: A storage system is described. The storage system may include a plurality of storage tiers, each including at least one storage device, each storage device including storage and a controller. Metadata storage may store metadata for an image stored in the plurality of storage tiers, which includes a location in the plurality of storage tiers where the image is stored. A receiver may receive a request to access the image from a host. Retrieval software, executed by a processor, may retrieve the image from the plurality of storage tiers using the location where the image is stored. A transmitter may transmit the image to the host.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Inventors: Sompong Paul OLARIG, William David SCHWADERER, Chandranil CHAKRABORTTII
  • Patent number: 10230398
    Abstract: A system and method for performing erasure code data protection and recovery computations using simple arithmetic and data manipulation functions. Other embodiments set forth techniques for using the computation functions with a multiplicity of compact one-dimension table lookup operations. A set of assigned multi-threaded processor threads perform computations on data values in parallel to generate erasure code data protection information and to perform data recovery operations using available data and the data protection information. During normal operations, in one embodiment, threads may perform parallel computations using a small set of simple arithmetic operations and data manipulation functions. In other embodiments, the threads may also use a multiplicity of compact one-dimension lookup tables stored within the multi-threaded processor or otherwise accessible by the multi-threaded processor to perform the computations.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: William David Schwaderer
  • Publication number: 20180054217
    Abstract: A system and method for performing erasure code data protection and recovery computations using simple arithmetic and data manipulation functions. Other embodiments set forth techniques for using the computation functions with a multiplicity of compact one-dimension table lookup operations. A set of assigned multi-threaded processor threads perform computations on data values in parallel to generate erasure code data protection information and to perform data recovery operations using available data and the data protection information. During normal operations, in one embodiment, threads may perform parallel computations using a small set of simple arithmetic operations and data manipulation functions. In other embodiments, the threads may also use a multiplicity of compact one-dimension lookup tables stored within the multi-threaded processor or otherwise accessible by the multi-threaded processor to perform the computations.
    Type: Application
    Filed: February 13, 2017
    Publication date: February 22, 2018
    Inventor: William David Schwaderer
  • Patent number: 9898202
    Abstract: A system and method for using a Solid State Drive (SSD) (505) are described. Reception circuitry (510) may receive write requests (1610, 1615, 1620, 1625) and invalidate requests (1630, 1635, 1640) from a first stream (305, 320, 335, 350). The write requests (1610, 1615, 1620, 1625) may request that data be written to storage (520) on the SSD (505); invalidate requests (1630, 1635, 1640) may invalidate data written to the storage (520). A statistics calculation logic (1705) may calculate statistics (1410, 1415, 1510) for the stream based on the write requests (1610, 1615, 1620, 1625) and the invalidate requests (1630, 1635, 1640). A performance logic (1710) may use the calculated statistics (1410, 1415, 1510) to improve the performance of the SSD (505).
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jason Martineau, William David Schwaderer, Changho Choi
  • Publication number: 20170235486
    Abstract: A system and method for using a Solid State Drive (SSD) (505) are described. Reception circuitry (510) may receive write requests (1610, 1615, 1620, 1625) and invalidate requests (1630, 1635, 1640) from a first stream (305, 320, 335, 350). The write requests (1610, 1615, 1620, 1625) may request that data be written to storage (520) on the SSD (505); invalidate requests (1630, 1635, 1640) may invalidate data written to the storage (520). A statistics calculation logic (1705) may calculate statistics (1410, 1415, 1510) for the stream based on the write requests (1610, 1615, 1620, 1625) and the invalidate requests (1630, 1635, 1640). A performance logic (1710) may use the calculated statistics (1410, 1415, 1510) to improve the performance of the SSD (505).
    Type: Application
    Filed: May 4, 2016
    Publication date: August 17, 2017
    Inventors: Jason MARTINEAU, William David SCHWADERER, Changho CHOI