Abstract: The present disclosure relates to embodiments of bus interface systems capable of dealing with the tougher half clock cycle of SREAD commands in the new mobile industry processor interface (MIPI) radio frequency front end (RFFE) version 2.0 standard. With regard to the slave bus controllers of the bus interface systems disclosed herein, the slave bus controller is configured to operate the slave bus driver such that the data bus line is driven towards a minimum voltage level in response to a final clock edge of the clock signal during the bus park subframe. To ensure compliance with the MIPI RFFE version 2.0 standard, the slave bus controller is configured to detect when the data bus line has been driven within a first voltage range after the final clock edge and continue driving the data bus line 16 even after the bus park half clock period is finished.

Abstract: A radio frequency front-end (RFFE) slave circuit and related apparatus are provided. The RFFE slave circuit may be coupled to a number of RFFE masters over an RFFE bus. The RFFE slave circuit may be configured by the RFFE masters for accessing, either concurrently or alternately, a number of sharable circuits in an envelope tracking (ET) circuit. The RFFE slave circuit may include common configuration circuitry configured to set a common configuration parameter(s) for a concurrently sharable circuit(s) in the ET circuit. The RFFE slave circuit may include private configuration circuitry configured to set a private configuration parameter(s) for an alternately sharable circuit(s) in the ET circuit. By employing the RFFE slave circuit to set the common and/or private configuration parameter(s) for the ET circuit, it may be possible to reduce processing delays in the RFFE bus, thus helping to improve efficiency of the ET circuit and/or the power amplifier(s).

Abstract: A communications system includes a single wire communications bus and a plurality of slave devices, each of the slave devices associated with a common slave identifier. The single wire communications bus is configured to receive a message comprising data, a slave identifier, and a register map address. A respective one of the plurality of slave devices selectively responds to the message if the slave identifier in the message is the same as the common slave identifier associated with the respective one of the plurality of slave devices and the register map address in the message is the same as the register map address associated with the respective one of the plurality of slave devices.

Abstract: A communications system includes a single wire communications bus and a plurality of slave devices, each of the slave devices associated with a common slave identifier. The single wire communications bus is configured to receive a message comprising data, a slave identifier, and a register map address. A respective one of the plurality of slave devices selectively responds to the message if the slave identifier in the message is the same as the common slave identifier associated with the respective one of the plurality of slave devices and the register map address in the message is the same as the register map address associated with the respective one of the plurality of slave devices.

Abstract: The present disclosure relates to embodiments of bus interface systems capable of dealing with the tougher half clock cycle of SREAD commands in the new mobile industry processor interface (MIPI) radio frequency front end (RFFE) version 2.0 standard. With regard to the slave bus controllers of the bus interface systems disclosed herein, the slave bus controller is configured to operate the slave bus driver such that the data bus line is driven towards a minimum voltage level in response to a final clock edge of the clock signal during the bus park subframe. To ensure compliance with the MIPI RFFE version 2.0 standard, the slave bus controller is configured to detect when the data bus line has been driven within a first voltage range after the final clock edge and continue driving the data bus line 16 even after the bus park half clock period is finished.

Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

Abstract: A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

Abstract: A direct current (DC)-DC converter, which includes a charge pump buck power supply and a buck power supply is disclosed. The charge pump buck power supply includes a charge pump buck converter, a first inductive element, and an energy storage element. The charge pump buck converter and the first inductive element are coupled in series between a DC power supply, such as a battery, and the energy storage element. The buck power supply includes a buck converter, a second inductive element, and the energy storage element. The buck converter and the second inductive element are coupled in series between the DC power supply and the energy storage element. As such, the charge pump buck power supply and the buck power supply share the energy storage element.

Abstract: A radio frequency (RF) switch semiconductor die and an RF supporting structure are disclosed. The RF switch semiconductor die is attached to the RF supporting structure. The RF switch semiconductor die has a first edge and a second edge, which may be opposite from the first edge. The RF supporting structure has a group of alpha supporting structure connection nodes, which is adjacent to the first edge; a group of beta supporting structure connection nodes, which is adjacent to the second edge; and an alpha AC grounding supporting structure connection node, which is adjacent to the second edge. When the group of alpha supporting structure connection nodes and the alpha AC grounding supporting structure connection node are active, the group of beta supporting structure connection nodes are inactive.

Abstract: RF PA circuitry and a DC-DC converter, which includes an RF PA envelope power supply and DC-DC control circuitry, are disclosed. The PA envelope power supply provides an envelope power supply signal to the RF PA circuitry. The DC-DC control circuitry has a DC-DC look-up table (LUT) structure, which has at least a first DC-DC LUT. The DC-DC control circuitry uses DC-DC LUT index information as an index to the DC-DC LUT structure to obtain DC-DC converter operational control parameters. The DC-DC control circuitry then configures the PA envelope power supply using the DC-DC converter operational control parameters. Using the DC-DC LUT structure provides flexibility in configuring the DC-DC converter for different applications, for multiple static operating conditions, for multiple dynamic operating conditions, or any combination thereof.

Abstract: The present disclosure relates to a flexible direct current (DC)-DC converter, which includes a charge pump buck power supply and a buck power supply. The charge pump buck power supply and the buck power supply are voltage compatible with one another at respective output inductance nodes to provide flexibility. In one embodiment of the DC-DC converter, capacitances at the output inductance nodes are at least partially isolated from one another by using at least an isolating inductive element between the output inductance nodes to increase efficiency. In an alternate embodiment of the DC-DC converter, the output inductance nodes are coupled to one another, such that the charge pump buck power supply and the buck power supply share a first inductive element, thereby eliminating the isolating inductive element, which reduces size and cost but may also reduce efficiency.

Abstract: Circuitry, which includes a direct current (DC)-DC converter having a first switching power supply is disclosed. The first switching power supply includes a first switching converter, an energy storage element, a first inductive element, which is coupled between the first switching converter and the energy storage element, and a first snubber circuit, which is coupled across the first inductive element. The first switching power supply receives and converts a DC power supply signal to provide a first switching power supply output signal based on a setpoint.

Abstract: A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

Abstract: Radio Frequency (RF) signal conditioning circuitry, which includes RF detection circuitry and RF attenuation circuitry is disclosed. The RF detection circuitry receives and detects an RF sample signal to provide an RF detection signal. The RF attenuation circuitry has an attenuation circuitry input, and receives and attenuates the RF sample signal via the attenuation circuitry input to provide an attenuated RF signal. The RF attenuation circuitry presents an attenuation circuitry input impedance at the attenuation circuitry input. The attenuated RF signal and the RF detection signal are provided concurrently.

Abstract: Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification.

Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

Abstract: A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first switching converter and the multi-stage filter form a feedback loop, which is used to regulate the first switching power supply output signal based on the setpoint. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

Abstract: Circuitry, which includes multi-mode multi-band radio frequency (RF) power amplification circuitry, power amplifier (PA) control circuitry, and a PA-digital communications interface (DCI) is disclosed according to one embodiment of the circuitry. The PA control circuitry is coupled between the amplification circuitry and the PA-DCI, which is coupled to a digital communications bus, and configures the amplification circuitry. The amplification circuitry includes at least a first RF input and multiple RF outputs, such that at least some of the RF outputs are associated with multiple communications modes and at least some of the RF outputs are associated with multiple frequency bands. Configuration of the amplification circuitry associates one RF input with one RF output, and is correlated with configuration information defined by at least a first defined parameter set. The PA control circuitry stores at least a first look-up table (LUT), which provides the configuration information.

Abstract: Radio frequency (RF) power amplifier (PA) circuitry, which transmits RF signals is disclosed. The RF PA circuitry includes a final stage, a final stage current digital-to-analog converter (IDAC), and a final stage temperature compensation circuit. A final stage current reference circuit may provide an uncompensated final stage reference current to the final stage temperature compensation circuit, which receives and temperature compensates the uncompensated final stage reference current to provide a final stage reference current. The final stage IDAC uses the final stage reference current in a digital-to-analog conversion to provide a final stage bias signal to bias the final stage. The temperature compensation provided by the final stage temperature compensation circuit is selectable.

Abstract: A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.