Patents by Inventor William Dewey

William Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11590241
    Abstract: Provided herein are nanoparticle conjugated synthetic opioid prodrugs that target the peripheral mu opioid receptor (MOR). The prodrugs exhibit long-lived bioavailability, do not compromise the analgesic effects of opioids administered for pain relief (and in some cases can be used for pain relief), and do not induce opioid withdrawal symptoms, when their use is discontinued. Certain of the prodrugs are especially useful for the prevention and/or treatment of unwanted opioid-induced side effects such as opioid-induced constipation (OIC).
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: February 28, 2023
    Assignee: Virginia Commonwealth University
    Inventors: Yan Zhang, Hu Yang, Dana Selley, William Dewey, Hamid Akbarali
  • Patent number: 11314916
    Abstract: An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: David J. Widiger, Steven Joseph Kurtz, Lewis William Dewey, III, Susan Elizabeth Cellier, Ronald Dennis Rose
  • Publication number: 20220035983
    Abstract: An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: David J. Widiger, Steven Joseph Kurtz, Lewis William Dewey, III, Susan Elizabeth Cellier, Ronald Dennis Rose
  • Patent number: 11176308
    Abstract: An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: David J. Widiger, Steven Joseph Kurtz, Susan Elizabeth Cellier, Lewis William Dewey, III, Ronald Dennis Rose
  • Patent number: 11119862
    Abstract: Method and apparatus for managing data in a distributed data storage system, such as but not limited to a cloud computing environment. In some embodiments, snapshots of a data set are uploaded from a source storage subsystem to a cloud store, along with intervening difference information volumes (DIVs). The DIVs are data structures that identify a set of updated data blocks that have been changed by the source storage subsystem between each successive pair of the snapshots. A reader subsystem requests and uses the latest DIV to request the latest set of changed data blocks from the cloud store, and uses the latest set of changed data blocks to update a previous snapshot to generate a copy of the most recent snapshot. The source and reader subsystems can comprise Internet of Things (IoT) devices, client devices, edge computing devices, etc. from different vendors and which utilize different protocols.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Seagate Technology LLC
    Inventors: Douglas William Dewey, Ian Robert Davies, Kenneth F. Day, III
  • Publication number: 20210205472
    Abstract: Provided herein are nanoparticle conjugated synthetic opioid prodrugs that target the peripheral mu opioid receptor (MOR). The prodrugs exhibit long-lived bioavailability, do not compromise the analgesic effects of opioids administered for pain relief (and in some cases can be used for pain relief), and do not induce opioid withdrawal symptoms, when their use is discontinued. Certain of the prodrugs are especially useful for the prevention and/or treatment of unwanted opioid-induced side effects such as opioid-induced constipation (OIC).
    Type: Application
    Filed: February 17, 2017
    Publication date: July 8, 2021
    Inventors: Yan ZHANG, Hu YANG, Dana SELLEY, William DEWEY, Hamid AKBARALI
  • Patent number: 10988481
    Abstract: Analogues of 6 ?/?-naltrexamine (NAQ) are provided. The analogues are selective, reversible antagonists of the mu opioid receptor (MOR) that exhibit good blood brain barrier penetration. The compounds are used in the treatment of opioid addiction and other diseases and conditions, including for the treatment of pain.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 27, 2021
    Assignee: Virginia Commonwealth University
    Inventors: Yan Zhang, Dana E. Selley, William Dewey, Hamid Abkarali
  • Publication number: 20210109814
    Abstract: Method and apparatus for managing data in a distributed data storage system, such as but not limited to a cloud computing environment. In some embodiments, snapshots of a data set are uploaded from a source storage subsystem to a cloud store, along with intervening difference information volumes (DIVs). The DIVs are data structures that identify a set of updated data blocks that have been changed by the source storage subsystem between each successive pair of the snapshots. A reader subsystem requests and uses the latest DIV to request the latest set of changed data blocks from the cloud store, and uses the latest set of changed data blocks to update a previous snapshot to generate a copy of the most recent snapshot. The source and reader subsystems can comprise Internet of Things (IoT) devices, client devices, edge computing devices, etc. from different vendors and which utilize different protocols.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Douglas William Dewey, Ian Robert Davies, Kenneth F. Day, III
  • Patent number: 10964701
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 10950301
    Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Jack T. Kavalieros
  • Patent number: 10896088
    Abstract: A method includes identifying, using a controller, a first data error at a first data block stored in page metadata, the first data block having a first block logical ID. The method also includes identifying a second data block having the first block logical ID. The method also includes copying the second data block to the first data block based on the identified second data block.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 19, 2021
    Assignee: Seagate Technology LLC
    Inventors: Gomathirajan Authoor Velayuthaperumal, Adam Thomas Wolinski, Jeffery L. Shellhamer, Ian Robert Davies, Douglas William Dewey
  • Patent number: 10783029
    Abstract: A storage system periodically replicates data to another storage system for data backup and protection. The storage system is configured to detect an irregularity potentially causing a fault in the storage system. Such a detected irregularity may a component failure in a storage device, a temperature change in a storage device, etc. In response to the detected irregularity, the storage system increases a replication rate of data to the backup storage system.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: September 22, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Stephen S. Huh, Ian Davies, Douglas William Dewey
  • Publication number: 20200159621
    Abstract: A method includes identifying, using a controller, a first data error at a first data block stored in page metadata, the first data block having a first block logical ID. The method also includes identifying a second data block having the first block logical ID. The method also includes copying the second data block to the first data block based on the identified second data block.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Gomathirajan Authoor Velayuthaperumal, Adam Thomas Wolinski, Jeffery L. Shellhamer, Ian Robert Davies, Douglas William Dewey
  • Patent number: 10644140
    Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Van Hoang Le, Gilbert William Dewey, Marko Radosavljevic, Rafael Rios, Jack T. Kavalieros
  • Publication number: 20190393223
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Application
    Filed: March 31, 2017
    Publication date: December 26, 2019
    Inventors: Abhishek Anil SHARMA, Van H. LE, Gilbert William DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Yih WANG, Shriram SHIVARAMAN
  • Publication number: 20190308987
    Abstract: Peripherally selective compounds that modulate both the mu opioid receptor (MOR) and the kappa opioid receptor (KOR) are provided. The compounds are substituted derivatives of 6p-N-heterocyclic naltrexamine (NAP) and are used in the treatment of diseases involving visceral pain such as irritable bowel syndrome (IBS), opioid induced constipation (OIC), and others.
    Type: Application
    Filed: May 26, 2017
    Publication date: October 10, 2019
    Inventors: Yan ZHANG, Dana SELLEY, William DEWEY, Hamid AKBARALI
  • Patent number: 10409682
    Abstract: The technology disclosed herein includes a method for dividing a body of user data into a plurality of data blocks, and writing the plurality of data blocks into chunk zones in parallel streams, the chunk zones located in a first ordered pool of storage devices. In some implementations, the method includes adding additional storage devices to the first ordered pool making a second ordered pool, including the first ordered pool, and writing the plurality of data blocks across the second ordered pool of storage devices, such that each of the storage devices including spare capacity. The method includes determining if a storage device fails, and seeking data for the data blocks on the failed storage device from of the other storage devices.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 10, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ian Davies, Ruiling Luo, Thomas George Wicklund, Kenneth F. Day, Douglas William Dewey
  • Publication number: 20190252020
    Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.
    Type: Application
    Filed: September 30, 2016
    Publication date: August 15, 2019
    Inventors: Rafael RIOS, Abhishek Anil SHARMA, Van H. LE, Gilbert William DEWEY, Jack T. KAVALIEROS
  • Publication number: 20190152982
    Abstract: Analogues of 6 ?/?-naltrexamine (NAQ) are provided. The analogues are selective, reversible antagonists of the mu opioid receptor (MOR) that exhibit good blood brain barrier penetration. The compounds are used in the treatment of opioid addiction and other diseases and conditions, including for the treatment of pain.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 23, 2019
    Inventors: Yan ZHANG, Dana E. SELLEY, William DEWEY, Hamid ABKARALI
  • Publication number: 20190131437
    Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.
    Type: Application
    Filed: June 30, 2016
    Publication date: May 2, 2019
    Inventors: Van Hoang LE, Gilbert William DEWEY, Marko RADOSAVLJEVIC, Rafael RIOS, Jack T. KAVALIEROS