Patents by Inventor William Ditto

William Ditto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11487926
    Abstract: A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 1, 2022
    Assignee: North Carolina State University
    Inventors: Behnam Kia, William Ditto, Yaman Dalal, Ravikanth Somsole, Siva Rama Maruthi Ven Donepudi Krishna Sesha Sai, Allen R. Mendes, Akshay Parnami, Robin George
  • Publication number: 20210294954
    Abstract: A system can include a nonlinear circuit and a voltage decoder. The nonlinear circuit can perform an operation on an input voltage. The operation can be changed. A voltage decoder can be communicatively coupled to the nonlinear circuit for receiving an output voltage from the nonlinear circuit that results from the operation performed on the input voltage. The voltage decoder can compare the output voltage to a threshold voltage and determine a result of the operation.
    Type: Application
    Filed: August 29, 2017
    Publication date: September 23, 2021
    Inventors: Behnam Kia, William Ditto, Yaman Dalal, Ravikanth Somsole, Siva Rama Maruthi Ven Donepudi Krishna Sesha Sai, Allen R. Mendes, Akshay Parnami, Robin George
  • Patent number: 9425799
    Abstract: The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least one chaotic circuit block, a bias voltage generating circuit block, and a threshold circuit block. The encoding circuit block converts a plurality of digital inputs to an analog output. The plurality of digital inputs may comprise at least one data input and at least one control input. At least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to at least one chaotic circuit as the input signal at each iteration. The bias voltage generating circuit block converts a plurality of binary control inputs to a bias voltage. The threshold circuit block compares the output signal with a predetermined threshold, thereby generating a digital signal.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 23, 2016
    Assignee: University of Hawaii
    Inventors: William Ditto, Behnam Kia
  • Publication number: 20160087634
    Abstract: The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least one chaotic circuit block, a bias voltage generating circuit block, and a threshold circuit block. The encoding circuit block converts a plurality of digital inputs to an analog output. The plurality of digital inputs may comprise at least one data input and at least one control input. At least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to at least one chaotic circuit as the input signal at each iteration. The bias voltage generating circuit block converts a plurality of binary control inputs to a bias voltage. The threshold circuit block compares the output signal with a predetermined threshold, thereby generating a digital signal.
    Type: Application
    Filed: March 6, 2015
    Publication date: March 24, 2016
    Inventors: William Ditto, Behnam Kia
  • Patent number: 9064091
    Abstract: The present invention provides systems and methods for coupled dynamical systems for chaos computing. For example, a system for the coupled dynamical system comprises a first, second, and third circuit. The first circuit comprising a plurality of single dynamical systems forms a coupled dynamical system that reduces local noises in the plurality of single dynamical systems by diffusing the local noises across the coupled dynamical system. The second circuit, connected to the first circuit, receives the data and control inputs and builds an encoding map that translates the data and control inputs to an initial condition on an unstable manifold of the plurality of single dynamical systems in the coupled dynamical system. After the coupled dynamical system evolves, a third circuit, connected to the first circuit, samples a state of one of the plurality of single dynamical systems in the coupled dynamical system and builds a decoding map.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: June 23, 2015
    Assignee: University of Hawaii
    Inventors: William Ditto, Behnam Kia, Sarvenaz Kia
  • Publication number: 20140359256
    Abstract: The present invention provides systems and methods for coupled dynamical systems for chaos computing. For example, a system for the coupled dynamical system comprises a first, second, and third circuit. The first circuit comprising a plurality of single dynamical systems forms a coupled dynamical system that reduces local noises in the plurality of single dynamical systems by diffusing the local noises across the coupled dynamical system. The second circuit, connected to the first circuit, receives the data and control inputs and builds an encoding map that translates the data and control inputs to an initial condition on an unstable manifold of the plurality of single dynamical systems in the coupled dynamical system. After the coupled dynamical system evolves, a third circuit, connected to the first circuit, samples a state of one of the plurality of single dynamical systems in the coupled dynamical system and builds a decoding map.
    Type: Application
    Filed: March 21, 2014
    Publication date: December 4, 2014
    Inventors: William Ditto, Behnam Kia, Sarvenaz Kia
  • Publication number: 20060091905
    Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
    Type: Application
    Filed: December 15, 2005
    Publication date: May 4, 2006
    Applicants: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William Ditto, Krishnamurthy Murali, Sudeshna Sinha
  • Publication number: 20050073337
    Abstract: A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Applicant: University of Florida
    Inventors: William Ditto, Krishnamurthy Murali, Sudeshna Sinha
  • Patent number: 6285249
    Abstract: A controlled stochastic resonance circuit applies stochastic resonance to bias a nonlinear device with a control signal having a selected amplitude, frequency, and phase to enhance or suppress the response of the device to a periodic signal embedded in noise.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: September 4, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Adi R. Bulsara, Frank E. Gordon, Mario E. Inchiosa, Markus Loecher, Luca Gammaitoni, Peter Haenggi, Kurt Arn Wiesenfeld, William Ditto, Joseph Neff