Patents by Inventor William Dostalik

William Dostalik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070210421
    Abstract: The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Haowen Bu, Anand Krishnan, Ting Tsui, William Dostalik, Rajesh Khamankar
  • Publication number: 20060068594
    Abstract: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch on an anti-reflective layer 170 and a portion of a hardmask layer 140, 150 to form an opening 162 in the substrate 100. The first etch is designed to be selective to a remaining portion of the hardmask layer 140, 150. A second etch, which is different from the first etch, is conducted on a remaining portion of the hardmask 140, 150, and it is designed to be less selective than the first etch to the remaining portion of the hardmask 140, 150. The first etch allows polymer to build up on the sidewalls of the opening 162, and the polymer substantially remains on the sidewalls during the second etch.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 30, 2006
    Applicant: Texas Instruments, Inc.
    Inventor: William Dostalik
  • Publication number: 20060068592
    Abstract: The present invention provides a method for etching a substrate 100. The method includes conducting a first etch through a dielectric layer 130 located over an etch-stop layer 140, the dielectric layer having a photoresist layer 170 located thereover and the first etch being selective to the etch-stop layer 140. A second etch different from the first etch is conducted on the etch-stop layer 120, the second etch including nitrogen and at least one fluorocarbon gas, such that the ratio of nitrogen to carbon in the etchant is greater than about 5:1.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Applicant: Texas Instruments, Inc.
    Inventor: William Dostalik
  • Publication number: 20050112898
    Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
    Type: Application
    Filed: November 25, 2003
    Publication date: May 26, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: K.R. Udayakumar, Ted Moise, Scott Summerfelt, Martin Albrecht, William Dostalik, Francis Celii