Patents by Inventor William Duggan

William Duggan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10884968
    Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Bradley Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan
  • Patent number: 10783100
    Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Matthew J. Adiletta, Brad Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan
  • Publication number: 20200073846
    Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.
    Type: Application
    Filed: March 27, 2019
    Publication date: March 5, 2020
    Inventors: Matthew J. Adiletta, Bradley Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mizra, Jose Niell, Thomas E. Willis, William Duggan
  • Publication number: 20200065271
    Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.
    Type: Application
    Filed: March 27, 2019
    Publication date: February 27, 2020
    Inventors: Matthew J. Adiletta, Brad Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan
  • Patent number: 8154305
    Abstract: Certain embodiments of the invention may include systems, methods, and apparatus for providing connection fault self-monitoring with DC bias current. According to an example embodiment of the invention, a method is provided for obtaining measurements and detecting connectivity faults associated with a voltage mode sensor. The method can include coupling a DC bias current into a circuit. The circuit includes a voltage mode sensor, and the voltage mode sensor can output a time varying signal. The method can also include setting a nominal level of the DC bias current, monitoring a voltage associated with the DC bias current, and determining circuit connectivity status based at least in part on monitoring the voltage.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: April 10, 2012
    Assignee: General Electric Company
    Inventors: Roy Anthony Carter, William Duggan Brackman, Jr., John Robert Booth
  • Publication number: 20120013345
    Abstract: Certain embodiments of the invention may include systems, methods, and apparatus for providing connection fault self-monitoring with DC bias current. According to an example embodiment of the invention, a method is provided for obtaining measurements and detecting connectivity faults associated with a voltage mode sensor. The method can include coupling a DC bias current into a circuit. The circuit includes a voltage mode sensor, and the voltage mode sensor can output a time varying signal. The method can also include setting a nominal level of the DC bias current, monitoring a voltage associated with the DC bias current, and determining circuit connectivity status based at least in part on monitoring the voltage.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Roy Anthony Carter, William Duggan Brackman, JR., John Robert Booth
  • Patent number: 6618235
    Abstract: A voltage transient suppression circuit for power electronic circuits comprising: a snubber circuit having a resistor and a first and second capacitive element connected in series with a switching power semiconductor; and a sensing logic device connected in parallel with the snubber circuit; the logic circuit being configured to receive voltage signals indicative of said first and second capacitive elements.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: September 9, 2003
    Assignee: General Electric Company
    Inventors: Robert Gregory Wagoner, Fred Henry Boettner, William Duggan Brackman, Jr., James Michael Nowak
  • Patent number: D504281
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 26, 2005
    Assignee: Inline Plastics Corporation
    Inventor: James William Duggan