Abstract: Information regarding memory access by other nodes within a coherency controller of a node is locally stored. The coherency controller receives a transaction relating a line of local memory of the node. In response to locally determining that the line of the local memory is not being cached by another node and/or has not been modified by another node, the coherency controller processes the transaction without accessing tag directory information regarding the line. A table within the controller may store entries corresponding to local memory sections. Each entry includes a count value tracking a number of lines of the section being cached by other nodes, and a count value tracking a number of lines of the section that have been modified by other nodes. The table may also include flags corresponding to the sections, each flag indicating the validity of the section's contents.

Abstract: The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.

Abstract: The local storage of information regarding memory access by other nodes within a coherency controller of a node is disclosed. The coherency controller receives a transaction relating a line of local memory of the node. In response to locally determining that the line of the local memory is not being cached by another node and/or has not been modified by another node, the coherency controller processes the transaction without accessing tag directory information regarding the line. A table within the controller may store entries corresponding to local memory sections. Each entry includes a count value tracking a number of lines of the section being cached by other nodes, and a count value tracking a number of lines of the section that have been modified by other nodes. The table may also include flags corresponding to the sections, each flag indicating the validity of the section's contents.

Abstract: The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.