Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: An integrated circuit can include a processor system configured to execute program code, wherein the processor system is hard-wired. The IC also can include programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system and can be configured to implement a power off procedure under the control of the processor system.

Abstract: A multiplier-accumulator includes a pre-adder, a multiplier, an accumulator, multiplexing logic, and control logic. The pre-adder is configured to sum a first input and a second input to produce a pre-sum output. The multiplier is configured to multiply a third input and the pre-sum output to produce a product output. The accumulator is configured to sum a pair of accumulator inputs to produce a sum output. The multiplexer is configured to select the pair of accumulator inputs from a plurality of multiplexer inputs, where the plurality of multiplexer inputs includes the product output and the sum output. The control logic is configured to control operation of the pre-adder, the accumulator, and the multiplexer logic. In an example, each of the first input, the second input, the third input, and the sum output is coupled to programmable interconnect of a programmable logic device.

Abstract: A programmable logic device includes a block random access memory (“BRAM”) that is split into two first in, first out (“FIFO”) memory arrays. Two sets of FIFO control logic and FIFO ports are associated with a single BRAM so that the BRAM can be operated as memory buffers for two independent FIFO memory systems.

Abstract: A programmable logic device includes a block random access memory (“BRAM”) with an embedded first in, first out (“FIFO”) controller. Embedding the FIFO logic in silicon, rather than configuring it in the fabric of the programmable logic device, provides a reliable, high-speed asynchronous FIFO memory system.

Abstract: A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series.

Abstract: A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series.